ACM2002EI-FL-YBW VER1
START AND STOP CONDITIONS:
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line,
while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the
clock is HIGH is defined as the STOP condition (P). The START and STOP conditions are illustrated in Fig.2.
SYSTEM CONFIGURATION:
The system configuration is illustrated in Fig.3.
Transmitter: the device, which sends the data to the bus
Master: the device, which initiates a transfer, generates clock signals and terminates a transfer
Slave: the device addressed by a master
Multi-Master: more than one master can attempt to control the bus at the same time without corrupting the
message
Arbitration: procedure to ensure that, if more than one master simultaneously tries to control the bus, only
one is allowed to do so and the message is not corrupted
Synchronization: procedure to synchronize the clock signals of two or more devices.
ACKNOWLEDGE:
Acknowledge is not Busy Flag in I2C interface.
Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH signal put on the bus
by the transmitter during which time the master generates an extra acknowledge related clock pulse. A slave
receiver which is addressed must generate an acknowledge after the reception of each byte. A master receiver
must also generate an acknowledge after the reception of each byte that has been clocked out of the slave
transmitter. The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse, so
that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold
times must be taken into consideration). A master receiver must signal an end-of-data to the transmitter by not
generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter
must leave the data line HIGH to enable the master to generate a STOP condition. Acknowledgement on the I2C
Interface is illustrated in Fig.4.
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