Single-In-Line Packages (SIP)
Capacitor Arrays
HOW TO ORDER
SP
A
1
1
A
561
K
A
A
AVX Style
Circuit
See Page 79
(A, B, C)
Lead
Style
Offset = 1
Centered = C
Voltage
Temperature
Coefficient
C0G = A
Capacitance
Code
(2 significant
digits + no.
Capacitance
Tolerance
C0G: K = ±10%
M = ±20%
Test
Number of
Leads
2 = 2
Level
50V = 5
100V = 1
A = Standard
X7R = C
3 = 3
Z5U = E
of zero)
X7R: K = ±10%
M = ±20%
Z = +80%,-20%
Z5U: M = ±20%
Z = +80%,-20%
P = GMV
(+100,-0%)
4 = 4
5 = 5
6 = 6
7 = 7
8 = 8
9 = 9
A = 10
B = 11
C = 12
D = 13
E = 14
10 pF = 100
100 pF = 101
1,000 pF = 102
22,000 pF = 223
220,000 pF = 224
1 µF = 105
10 µF = 106
100 µF = 107
*For dimensions, voltages, or capacitance values not specified, please contact factory.
Maximum Capacitance*
50V
100V
C0G
X7R
Z5U
2200 pF
0.10 µF
0.39 µF
1500 pF
0.033 µF
0.10 µF
AVX IS QUALIFIED TO THE FOLLOWING DSCC DRAWINGS
SPECIFICATION #
DESCRIPTION
BX-100 VDC
C0G-100 VDC
BX-100 VDC
C0G-100 VDC
BX-100 VDC
BX-100 VDC
C0G-100 VDC
CIRCUIT
LEADS
CAPACITANCE RANGE
87112
A
A
C
C
B
A
B
8
8
1000 pF
10 pF
-
-
-
0.1 µF
820 pF
0.1 µF
87116
87119
10
10
8
1000 pF
87120
10 pF - 1000 pF
87122
1000 pF
1000 pF
10 pF
-
-
-
0.1 µF
0.1 µF
820 pF
88019
10
8
89086
80
KYOCERA AVX [ KYOCERA AVX ]
