The AL440B FIFO memory provides
completely independent 8bit input and output
ports that can operate at a maximum speed of
80 MHz. The built-in address and pointer
control circuits provide a straightforward bus
interface to serially read/write memory that
can reduce inter-chip design efforts.
write ports control signals, such as Read/Write
Enable, Input/Output Enable.., can be either
active low or high by pulling /PLRTY signal
to high or low respectively.
Window data read/write is supported in the
AL440B to benefit the designing effort for
applications such as PIP display. The window
mode is enabled by driving low on /SDAEN
signal. A serial bus can program built-in
registers to set up coordinates of the window
and the settings take effect following by next
read/write reset pulse. Window mirroring can
cooperate with the window mode data access
to flip window data in x or y direction. When
window-mirroring function is turned on, write
data can be stored in reverse sequence.
Manufactured using
a
state-of-the-art
embedded high density memory cell array, the
AL440B uses high performance process
technologies with extended controller
functions (write mask, read skip, window
mode read/write .. etc.), allowing easy
operation of non-linearity and regional
read/write FIFO for PIP, Digital TV, security
system and video camera applications.
The 4Mbits AL440B is configured as 512k x
8-bit FIFO to accommodate NTSC, PAL or
up to SVGA resolution. Running at high
speed (80Mhz maximum) and low power
consumption AC characteristics (3.3V power
supply) allow the high performance and high
quality application capability for designs such
as HDTV.
Available as a 44-pin TSOP (II), the small
footprint allows product designers to keep real
estate to a minimum.
Additional manipulation is produced by the
Input/Output Enable control signals. The
application can use input enable to control
whether new data is going to be written over
the old data or not. For read data, the output
enable signal can control whether data is going
to be skipped during the read operation.
DISTRIBUTED BY:
The Input/Output Ready flags report the
FIFO status. The flags can be used to indicate
Fullness/Emptiness of the FIFO capacity.
Expanding AL440B data bus width is also
possible by using multiple AL440B chips in
parallel.
To have better control flexibility in the inter-
chip design, the polarities of the AL440B
control signals are selectable. The read and
AVERLOGIC TECHNOLOGIES, INC. TEL: 1 408 361-0400
e-mail: sales@averlogic.com
URL: www.averlogic.com
November 11, 2002
AVERLOGIC [ AVERLOGIC TECHNOLOGIES INC ]
