欢迎访问ic37.com |
会员登录 免费注册
发布采购

HCPL-5200 参数 Datasheet PDF下载

HCPL-5200图片预览
型号: HCPL-5200
PDF下载: 下载PDF文件 查看货源
内容描述: 密封式低中频,宽VCC逻辑门光电耦合器 [Hermetically Sealed Low IF, Wide VCC, Logic Gate Optocouplers]
分类和应用: 光电
文件页数/大小: 14 页 / 365 K
品牌: AVAGO [ AVAGO TECHNOLOGIES LIMITED ]
 浏览型号HCPL-5200的Datasheet PDF文件第6页浏览型号HCPL-5200的Datasheet PDF文件第7页浏览型号HCPL-5200的Datasheet PDF文件第8页浏览型号HCPL-5200的Datasheet PDF文件第9页浏览型号HCPL-5200的Datasheet PDF文件第11页浏览型号HCPL-5200的Datasheet PDF文件第12页浏览型号HCPL-5200的Datasheet PDF文件第13页浏览型号HCPL-5200的Datasheet PDF文件第14页  
Typical Characteristics  
ꢞllꢀtꢏꢘicalꢀvalueꢂꢀareꢀatꢀꢁ ꢀ=ꢀꢔꢊꢑCꢌꢀꢖ ꢀ=ꢀꢊꢀꢖꢌꢀꢃ ꢀ=ꢀꢊꢀmꢞꢀunleꢂꢂꢀotherwiꢂeꢀꢂꢘecified.  
CC  
ꢇ(ꢝN)  
Parameter  
Symbol  
Test Conditions  
CCꢀ=ꢀꢊꢀꢖ  
Typ.  
0.07  
ꢅꢓ.ꢔꢊ  
Units  
mꢞ  
Fig.  
Notes  
ꢃnꢘutꢀCurrentꢀꢍꢏꢂtereꢂiꢂ  
ꢍYS  
ꢃnꢘutꢀDiodeꢀꢁemꢘeratureꢀ  
Coefficient  
Dꢇ  
Dꢞ  
ꢀ=ꢀꢉꢀmꢞ  
mꢖꢛꢑC  
W
ꢘꢇ  
ꢘꢇ  
nꢂ  
nꢂ  
ꢆeꢂiꢂtanceꢀ(ꢃnꢘutꢅꢝutꢘut)  
ꢃꢅꢝ  
Cꢃꢅꢝ  
CꢃN  
tr  
ꢃꢅꢝꢀ=ꢀꢊ00ꢀꢖdc  
�ꢀ=ꢀꢓꢀMꢍz  
ꢓ0ꢓꢈ  
ꢔ.0  
ꢔ0  
ꢔꢌꢀꢉ  
ꢔꢌꢀꢉ  
ꢔꢌꢀꢓ0  
Caꢘacitanceꢀ(ꢃnꢘutꢅꢝutꢘut)  
ꢃnꢘutꢀCaꢘacitance  
ꢀ=ꢀ0ꢀꢖꢌꢀ�ꢀ=ꢀꢓꢀMꢍz  
ꢝutꢘutꢀꢆiꢂeꢀꢁimeꢀ(ꢓ0ꢅ90%)  
ꢝutꢘutꢀꢇallꢀꢁimeꢀ(90ꢅꢓ0%)  
ꢊ  
ꢊꢌꢀ7  
ꢊꢌꢀ7  
t�  
ꢓ0  
Single Channel Product Only  
ꢝutꢘutꢀEnableꢀꢁimeꢀtoꢀꢄogicꢀꢍigh  
ꢝutꢘutꢀEnableꢀꢁimeꢀtoꢀꢄogicꢀꢄow  
ꢝutꢘutꢀDiꢂableꢀꢁimeꢀ�romꢀꢄogicꢀꢍigh  
ꢝutꢘutꢀDiꢂableꢀꢁimeꢀ�romꢀꢄogicꢀꢄow  
Multi-Channel Product Only  
tPZꢍ  
tPZꢄ  
tPꢍZ  
tPꢄZ  
ꢈ0  
ꢈ0  
ꢊ  
ꢊꢊ  
nꢂ  
nꢂ  
nꢂ  
nꢂ  
ꢃnꢘutꢅꢃnꢘutꢀꢃnꢂulationꢀꢄeakageꢀꢀ  
Current  
ꢃꢅꢃ  
ꢆꢍꢀꢀ6ꢊ%ꢌꢀ  
ꢃꢅꢃꢀ=ꢀꢊ00ꢀꢖꢌꢀtꢀ=ꢀꢊꢀꢂ  
0.ꢊ  
nꢞ  
9
ꢓ0ꢓꢈ  
ꢓ.ꢊ  
9
9
W
ꢆeꢂiꢂtanceꢀ(ꢃnꢘutꢅꢃnꢘut)  
Caꢘacitanceꢀ(ꢃnꢘutꢅꢃnꢘut)  
ꢃꢅꢃ  
Cꢃꢅꢃ  
ꢃꢅꢃꢀ=ꢀꢊ00ꢀꢖ  
�ꢀ=ꢀꢓꢀMꢍz  
ꢘꢇ  
Noteꢂꢙ  
ꢓ.ꢀ PeakꢀꢇorwardꢀꢃnꢘutꢀCurrentꢀꢘulꢂeꢀwidthꢀ<ꢀꢊ0ꢀꢜꢂꢀatꢀꢓꢀꢎꢍzꢀmaꢗimumꢀreꢘetitionꢀrate.  
ꢔ.ꢀ Eachꢀchannelꢀo�ꢀaꢀmultichannelꢀdevice.  
ꢈ.ꢀ Durationꢀo�ꢀoutꢘutꢀꢂhortꢀcircuitꢀtimeꢀnotꢀtoꢀeꢗceedꢀꢓ0ꢀmꢂ.  
.ꢀ ꢞllꢀdeviceꢂꢀareꢀconꢂideredꢀtwoꢅterminalꢀdeviceꢂꢙꢀmeaꢂuredꢀbetweenꢀallꢀinꢘutꢀleadꢂꢀorꢀterminalꢂꢀꢂhortedꢀtogetherꢀandꢀallꢀoutꢘutꢀleadꢂꢀorꢀterꢅ  
minalꢂꢀꢂhortedꢀtogether.  
ꢊ.ꢀ ꢁhiꢂꢀiꢂꢀaꢀmomentarꢏꢀwithꢂtandꢀteꢂtꢌꢀnotꢀanꢀoꢘeratingꢀcondition.  
6.ꢀ CM ꢀiꢂꢀtheꢀmaꢗimumꢀrateꢀo�ꢀriꢂeꢀo�ꢀtheꢀcommonꢀmodeꢀvoltageꢀthatꢀcanꢀbeꢀꢂuꢂtainedꢀwithꢀtheꢀoutꢘutꢀvoltageꢀinꢀtheꢀlogicꢀlowꢀꢂtateꢀ(ꢖ ꢀ<ꢀ0.ꢉꢀ  
ꢖ).ꢀCM ꢀiꢂꢀtheꢀmaꢗimumꢀrateꢀo�ꢀ�allꢀo�ꢀtheꢀcommonꢀmodeꢀvoltageꢀthatꢀcanꢀbeꢀꢂuꢂtainedꢀwithꢀtheꢀoutꢘutꢀvoltageꢀinꢀtheꢀlogicꢀhighꢀꢂtateꢀ(ꢖ ꢀꢚꢀ  
ꢔ.0ꢀꢖ).  
7.ꢀ t ꢀꢘroꢘagationꢀdelaꢏꢀiꢂꢀmeaꢂuredꢀ�romꢀtheꢀꢊ0%ꢀꢘointꢀonꢀtheꢀleadingꢀedgeꢀo�ꢀtheꢀinꢘutꢀꢘulꢂeꢀtoꢀtheꢀꢓ.ꢈꢀꢖꢀꢘointꢀonꢀtheꢀleadingꢀedgeꢀo�ꢀtheꢀ  
Pꢍꢄ  
outꢘutꢀꢘulꢂe.ꢀꢁheꢀt ꢀꢘroꢘagationꢀdelaꢏꢀiꢂꢀmeaꢂuredꢀ�romꢀtheꢀꢊ0%ꢀꢘointꢀonꢀtheꢀtrailingꢀedgeꢀo�ꢀtheꢀinꢘutꢀꢘulꢂeꢀtoꢀtheꢀꢓ.ꢈꢀꢖꢀꢘointꢀonꢀtheꢀ  
Pꢄꢍ  
trailingꢀedgeꢀo�ꢀtheꢀoutꢘutꢀꢘulꢂe.  
ꢉ.ꢀ Meaꢂuredꢀbetweenꢀeachꢀinꢘutꢀꢘairꢀꢂhortedꢀtogetherꢀandꢀallꢀoutꢘutꢀconnectionꢂꢀ�orꢀthatꢀchannelꢀꢂhortedꢀtogether.  
9.ꢀ Meaꢂuredꢀbetweenꢀadjacentꢀinꢘutꢀꢘairꢂꢀꢂhortedꢀtogetherꢀ�orꢀeachꢀmultichannelꢀdevice.  
ꢓ0.ꢀZeroꢅbiaꢂꢀcaꢘacitanceꢀmeaꢂuredꢀbetweenꢀtheꢀꢄEDꢀanodeꢀandꢀcathode.  
ꢓꢓ.ꢀStandardꢀꢘartꢂꢀreceiveꢀꢓ00%ꢀteꢂtingꢀatꢀꢔꢊꢑCꢀ(Subgrouꢘꢂꢀꢓꢀandꢀ9).ꢀSMDꢌꢀClaꢂꢂꢀꢍꢀandꢀClaꢂꢂꢀꢎꢀꢘartꢂꢀreceiveꢀꢓ00%ꢀteꢂtingꢀatꢀꢔꢊꢌꢀꢓꢔꢊꢌꢀandꢀ–ꢊꢊꢑCꢀ  
(Subgrouꢘꢂꢀꢓꢀandꢀ9ꢌꢀꢔꢀandꢀꢓ0ꢌꢀꢈꢀandꢀꢓꢓꢌꢀreꢂꢘectivelꢏ).  
ꢓꢔ.ꢀParameterꢂꢀareꢀteꢂtedꢀaꢂꢀꢘartꢀo�ꢀdeviceꢀinitialꢀcharacterizationꢀandꢀa�terꢀdeꢂignꢀandꢀꢘroceꢂꢂꢀchangeꢂ.ꢀParameterꢂꢀguaranteedꢀtoꢀlimitꢂꢀꢂꢘeciꢅ  
fiedꢀ�orꢀallꢀlotꢂꢀnotꢀꢂꢘecificallꢏꢀteꢂted.  
10