V
V
V
V
E
V
V
V
V
E
IN+
IN+
0.1
μF
7 V
–
0.1
μF
–
+
V
V
IN-
LED2+
IN-
LED2+
+
5 V
+
–
I
30 V
DSCHG
DESAT
DESAT
CC1
CC1
GND1
V
GND1
V
CC2
CC2
0.1 μF
SWEEP
RESET
FAULT
V
C
RESET
FAULT
V
C
+
+
–
V
OUT
–
V
V
OUT
OUT
30 V
0.1 μF
0.1 μF
V
V
V
V
LED1+
EE
LED1+
EE
V
V
V
V
LED1-
EE
LED1-
EE
Figure 42. IDSCHG test circuit.
Figure 43. UVLO threshold test circuit.
V
IN
V
V
E
V
V
V
V
E
IN+
IN+
IN-
–
0.1 μF
–
+
–
+
V
V
LED2+
V
IN-
LED2+
+
0.1
μF
0.1
μF
15 V
30 V
SWEEP
V
DESAT
DESAT
CC1
CC1
–
+
GND1
V
GND1
V
CC2
CC2
0.1 μF
0.1 μF
5 V
RESET
FAULT
V
C
RESET
FAULT
V
C
0.1
μF
V
OUT
+
–
+
–
V
V
OUT
OUT
10 mA
15 V
30 V
3 k
10 Ω
0.1 μF
V
V
V
V
V
0.1
μF
LED1+
EE
LED1+
EE
10
nF
V
V
V
LED1-
EE
LED1-
EE
Figure 44. DESAT threshold test circuit.
Figure 45. tPLH, tPHL, tr, tf test circuit.
V
V
V
V
V
V
V
V
E
IN+
E
IN+
0.1
μF
0.1
μF
0.1
μF
0.1
μF
–
+
–
+
V
V
V
V
IN
+
IN-
LED2+
IN
+
IN-
LED2+
–
–
30 V
30 V
5 V
5 V
DESAT
DESAT
CC1
CC1
GND1
V
GND1
V
CC2
CC2
0.1
μF
0.1
μF
3 k
FAULT
0.1
μF
RESET
FAULT
V
C
RESET
FAULT
V
C
0.1
μF
V
OUT
+
+
V
–
–
V
V
OUT
OUT
30 V
30 V
3 k
10 Ω
10 Ω
10
V
V
V
V
V
V
V
LED1+
EE
EE
LED1+
EE
EE
10
nF
nF
V
LED1-
LED1-
Figure 46. tDESAT(10%) test circuit.
Figure 47. tDESAT(FAULT) test circuit.
17
AVAGO [ AVAGO TECHNOLOGIES LIMITED ]
