HCPL-2201/11
HCPL-02XX
HCNW22XX
V
(+5 V)
CC2
80 Ω
V
(+5 V)
CC1
1
2
3
4
8
7
6
5
120 pF
1.1 kΩ
DATA OUTPUT
*
DATA INPUT
TTL OR LSTTL
UP TO 16 LSTTL LOADS
OR 4 TTL LOADS
1
* 0.1 µF BYPASS
2
Figure 13b. Recommended LSTTL to LSTTL circuit for applications requiring a maximum allowable propagation delay of 300 ns.
V
CC2
(4.5 TO 20 V)
HCPL-2201/11
HCPL-02XX
HCNW22XX
80 Ω*
R
L
V
(+5 V)
V
CC1
CC
1
2
3
4
8
7
6
5
HCPL-2201/11
HCPL-02XX
HCNW22XX
120 pF*
1.1 kΩ
CMOS
DATA OUTPUT
V
(+5 V)
CC1
**
1.1 kΩ
DATA INPUT
V
CC
1
2
3
4
8
7
6
5
TTL OR LSTTL
GND
DATA
INPUT
D1
TTL or
LSTTL
TOTEM
2
POLE
OUTPUT
GATE
1
V
5 V
10 V
15 V
20 V
R
L
* 120 pF PEAKING CAPACITOR
MAY BE OMITTED AND 80 Ω
RESISTOR MAY BE SHORTED
WHERE 500 ns PROPAGATION
DELAY IS SUFFICIENT.
CC2
GND
1.1 kΩ
2.37 kΩ
3.83 kΩ
5.11 kΩ
D1 (1N4150) REQUIRED FOR
ACTIVE PULL-UP DRIVER.
**0.1 µF BYPASS
Figure 14. LSTTL to CMOS interface circuit.
Figure 15. Alternative LED drive circuit.
HCPL-2201/11
HCPL-02XX
HCNW22XX
80 Ω*
V
(+5 V)
V
CC
CC
1
2
3
4
8
7
6
5
120 pF*
1.1 kΩ
4.7 kΩ
TTL OR LSTTL
DATA INPUT
GND
OPEN
COLLECTOR
GATE
* 120 pF PEAKING CAPACITOR
MAY BE OMITTED AND 80 Ω
RESISTOR MAY BE SHORTED
WHERE 500 ns PROPAGATION
DELAY IS SUFFICIENT.
Figure 16. Series LED drive with open collector gate (4.7 k resistor shunts IOH from the LED).
17
AVAGO [ AVAGO TECHNOLOGIES LIMITED ]
