SRAM
MT5C1008
Austin Semiconductor, Inc.
128K x 8 SRAM
PIN ASSIGNMENT
(Top View)
WITH DUAL CHIP ENABLE
32-Pin DIP (C, CW)
32-Pin CSOJ (SOJ)
32-Pin LCC (EC)
32-Pin SOJ (DCJ)
AVAILABLE AS MILITARY
SPECIFICATIONS
•SMD 5962-89598
•MIL-STD-883
VCC
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2 10
A1 11
A0 12
DQ1 13
DQ2 14
DQ3 15
1
2
3
4
5
6
7
8
9
32
VCC
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ1
DQ2
DQ3
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
31 A15
30 CE2
29 WE\
28 A13
27 A8
A15
CE2
WE\
A13
A8
A9
FEATURES
26 A9
A11
OE\
A10
CE\
DQ8
DQ7
DQ6
DQ5
DQ4
25 A11
24 OE\
23 A10
22 CE\
21 DQ8
20 DQ7
19 DQ6
18 DQ5
17 DQ4
• High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns
• Battery Backup: 2V data retention
• Low power standby
• High-performance, low-power CMOS process
• Single +5V (+10%) Power Supply
• Easy memory expansion with CE1\, CE2, and OE\
options.
VSS
16
32-Pin LCC (ECA)
32-Pin Flat Pack (F)
• All inputs and outputs are TTL compatible
4
3 2 1 32 31 30
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2 10
A1 11
A0 12
DQ1 13
DQ2 14
DQ3 15
VSS 16
1
2
3
4
5
6
7
8
9
32 VCC
31 A15
30 CE2
29 WE\
28 A13
27 A8
5
6
7
8
9
10
11
12
13
A7
A6
A5
A4
A3
A2
A1
A0
DQ1
29
28
27
26
25
24
23
22
21
WE
\
A13
A8
26 A9
A9
25 A11
24 OE\
23 A10
22 CE\
21 DQ8
20 DQ7
19 DQ6
18 DQ5
17 DQ4
A11
\
A10
CE1
OPTIONS
• Timing
MARKING
OE
\
DQ8
12ns access
15ns access
20ns access
25ns access
35ns access
45ns access
55ns access
70ns access
-12 (contact factory)
-15
14 15 16 17 18 19 20
-20
-25
-35
-45
-55*
-70*
GENERAL DESCRIPTION
The MT5C1008 SRAM employs high-speed, low power
CMOS designs using a four-transistor memory cell, and are
fabricated using double-layer metal, double-layer polysilicon
technology.
For design flexibility in high-speed memory
applications, this device offers dual chip enables (CE1\, CE2)
and output enable (OE\). These control pins can place the
outputs in High-Z for additional flexibility in system design.
All devices operate from a single +5V power supply and all
inputs and outputs are fully TTL compatible.
Writing to these devices is accomplished when write
enable (WE\) and CE1\ inputs are both LOW and CE2 is HIGH.
Reading is accomplished when WE\ and CE2 remain HIGH and
CE1\ and OE\ go LOW. The devices offer a reduced power
standby mode when disabled, allowing system designs to
achieve low standby power requirements.
• Package(s)•
Ceramic DIP (400 mil)
Ceramic DIP (600 mil)
Ceramic LCC
Ceramic LCC
Ceramic Flatpack
Ceramic SOJ
C
No. 111
No. 112
No. 207
No. 208
No. 303
No. 501
No. 507
CW
EC
ECA
F
DCJ
SOJ
Ceramic SOJ
• 2V data retention/low power
L
*Electrical characteristics identical to those provided for the 45ns
access devices.
The “L” version offers a 2V data retention mode, re-
ducing current consumption to 1mA maximum.
For more products and information
please visit our web site at
www.austinsemiconductor.com
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
MT5C1008
Rev. 6.5 7/02
1
AUSTIN [ AUSTIN SEMICONDUCTOR ]
