SRAM
MT5C1008
Austin Semiconductor, Inc.
FUNCTIONAL BLOCK DIAGRAM
VCC
GND
A
A
A
A
A
A
A
A
A
DQ8
DQ1
1,048,576-BIT
MEMORY ARRAY
(LSB)
CE1\
CE2
COLUMN DECODER
(LSB)
OE\
WE\
A A A A A A A A
POWER
DOWN
NOTE: The two least significant row address bits (A8 and A6) are encoded using gray code.
TRUTH TABLE
MODE
STANDBY
STANDBY
READ
READ
WRITE
OE\
X
X
L
H
CE1\
CE2
X
L
H
H
WE\
X
X
H
H
DQ
POWER
H
X
L
L
L
HIGH-Z STANDBY
HIGH-Z STANDBY
Q
HIGH-Z
D
ACTIVE
ACTIVE
ACTIVE
X
H
L
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
MT5C1008
Rev. 6.5 7/02
2