SRAM
AS8S128K32
Austin Semiconductor, Inc.
CAPACITANCE TABLE (V = ꢀV, f = 1 MHz, T = 25oC)
A
IN
SYMBOL
PARAMETER
MAX
UNITS
NOTES
CADD
A0 - A18 Capacitance
40
40
20
20
pF
pF
pF
pF
4
COE
OE\ Capacitance
4
4
4
CWE, CCE
CIO
WE\ and CE\ Capacitance
I/O 0- I/O 31 Capacitance
TRUTH TABLE
MODE
Read
Write
Standby
Not Selected
OE\
L
X
X
H
CE\
L
L
H
L
WE\
H
L
X
H
I/O
Q
D
POWER
ACTIVE
ACTIVE
STANDBY
ACTIVE
HIGH Z
HIGH Z
AC TEST CONDITIONS
TEST SPECIFICATIONS
Input pulse levels........................................VSS to 3V
Input rise and fall times..........................................5ns
Input timing reference levels.................................1.5V
Output reference levels........................................1.5V
Output load.............................................See Figures 1
I
OL
Current Source
Device
Under
Test
-
+
Vz = 1.5V
(Bipolar
Supply)
+
Ceff = 50pf
NOTES:
I
Current Source
OH
Vz is programable from -2V to + 7V.
IOL and IOH programmable from 0 to 16 mA.
Vz is typically the midpoint of VOH and VOL.
IOL and IOH are adjusted to simulate a typical resistive load
circuit.
Figure 1
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS8S128K32
Rev. 4.0 5/03
3
AUSTIN [ AUSTIN SEMICONDUCTOR ]
