SRAM
AS5C4008
Austin Semiconductor, Inc.
512K x 8 SRAM
SRAM MEMORY ARRAY
PIN ASSIGNMENT
(Top View)
AVAILABLE AS MILITARY
32-Pin DIP (CW), 32-Pin LCC (EC)
32-Pin SOJ (ECJ)
SPECIFICATION
• SMD 5962-95600
• SMD 5962-95613
• MIL STD-883
1
2
A18
A16
A14
A12
A7
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vcc
A15
A17
WE\
A13
A8
3
4
FEATURES
• High Speed: 12, 15, 17, 20, 25, 35 and 45ns
• High-performance, low power military grade device
• Single +5V ±10% power supply
• Easy memory expansion with CE\ and OE\ options
• All inputs and outputs are TTL-compatible
• Ease of upgradability from 1 Meg using the 32 pin
evolutionary version.
5
6
A6
7
A5
A9
8
A4
A11
OE\
A10
CE\
9
A3
10
11
12
13
14
15
16
A2
A1
A0
I/O7
I/O6
I/O5
I/O4
I/O3
I/O0
I/O1
I/O2
Vss
OPTIONS
• Timing
MARKING
12ns access
15ns access
17ns access
20ns access
25ns access
35ns access
45ns access
-12
-15
-17
-20
-25
-35
-45
32-Pin Flat Pack (F)
Vcc
A15
A17
WE\
A13
A8
1
A18
A16
A14
A12
A7
32
2
31
3
30
4
29
5
28
6
A6
27
• Operating Temperature Range
Military: -55oC to +125oC
Industrial: -40oC to +85oC
• Packages
Ceramic Dip (600 mil)
Ceramic Flatpack
Ceramic LCC
Ceramic SOJ
Ceramic LCC (contact factory)
• Options
A9
7
A5
26
XT
IT
A11
OE\
A10
CE\
8
A4
25
9
A3
24
10
11
12
13
14
15
16
A2
23
22
21
20
19
18
17
A1
CW
F
EC
ECJ
ECA
No. 112
No. 304
No. 209
No. 502
No. 208
I/O7
I/O6
I/O5
I/O4
I/O3
A0
I/O0
I/O1
I/O2
Vss
2V data retention/ low power
NOTE: Not all combinations of operating temperature, speed, data retention and
low power are necessarily available. Please contact factory for availability of specific part
number combinations.
L
32-Pin LCC (ECA)
4
3
2
32 31 30
29
GENERAL DESCRIPTION
5
6
7
8
9
A7
A6
A5
WE\
A13
A8
1
28
27
26
25
24
23
22
21
The AS5C4008 is a 4 megabit monolithic CMOS SRAM,
organized as a 512K x 8.
A4
A9
The evolutionary 32 pin device allows for easy upgrades from
the 1 meg SRAM.
For flexibility in high-speed memory applications, ASI offers
chip enable (CE\) and output enable (OE\) capabilities. These
enhancements can place the outputs in High-Z for additional flexibil-
ity in system design.
A3
A11
OE\
A10
CE\
I/O 7
10
11
12
13
A2
A1
A0
I/O0
14 15 16 17 18 19 20
Writing to these devices is accomplished when write enable (WE\)
and CE\ inputs are both LOW. Reading is accomplished when WE\
remains HIGH and CE\ and OE\ go LOW. This allows systems
designers to meet low standby power requirements.
All devices operate from a single +5V power supply and all
inputs are fully TTL-Compatible.
For more products and information
please visit our web site at
www.austinsemiconductor.com
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS5C4008
Rev. 6.2 06/05
1
AUSTIN [ AUSTIN SEMICONDUCTOR ]
