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AS5C2568ECW-12L/883C 参数 Datasheet PDF下载

AS5C2568ECW-12L/883C图片预览
型号: AS5C2568ECW-12L/883C
PDF下载: 下载PDF文件 查看货源
内容描述: 32K ×8 SRAM SRAM存储器阵列 [32K x 8 SRAM SRAM MEMORY ARRAY]
分类和应用: 存储静态存储器
文件页数/大小: 16 页 / 141 K
品牌: AUSTIN [ AUSTIN SEMICONDUCTOR ]
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Austin Semiconductor, Inc.
AC TEST CONDITIONS
Input pulse levels....................................................Vss to 3V
Input rise and fall times.....................................................5ns
Input timing reference level.............................................1.5V
Output reference level......................................................1.5V
Output load.................................................See figures 1 & 2
+5V
480
Q
255
30 pF
Q
255
MT5C2568
AS5C2568
+5V
480
5 pF
SRAM
NOTES
1.
2.
3.
All voltages referenced to V
SS
(GND).
-3V for pulse width < 20ns
I
CC
is dependent on output loading and cycle rates. The
specified value applies with the outputs unloaded, and
f=
1
Hz.
t
RC (MIN)
This parameter is guaranteed but not tested.
Test conditions as specified with the output loading as
shown in Fig. 1 unless otherwise noted.
t
HZCE,
t
HZOE and
t
HZWE are specified with CL = 5pF
as in Fig. 2. Transition is measured ±500mV typical from
steady state voltage, allowing for actual tester RC time
constant.
7.
Fig. 1
OUTPUT LOAD
EQUIVALENT
Fig. 2
OUTPUT LOAD
EQUIVALENT
4.
5.
6.
At any given temperature and voltage condition,
t
HZCE
is less than
t
LZCE, and
t
HZWE is less than
t
LZWE.
8. WE\ is HIGH for READ cycle.
9. Device is continuously selected. Chip enables and
output enables are held in their active state.
10. Address valid prior to, or coincident with, latest
occurring chip enable.
11.
t
RC = Read Cycle Time.
12. Chip enable (CE\) and write enable (WE\) can initiate and
terminate a WRITE cycle.
DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only)
DESCRIPTION
V
CC
for Retention Data
CE\ > (V
CC
-0.2V)
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
V
IN
> (V
CC
-0.2V)
or < 0.2V
I
CCDR
1
mA
CONDITIONS
SYM
V
DR
MIN
2
MAX
UNITS
V
NOTES
t
CDR
t
R
0
t
RC
--
ns
ns
4
4, 11
LOW Vcc DATA RETENTION WAVEFORM
V
CC
t
DATA RETENTION MODE
4.5V
CDR
V
DR
V
DR
> 2V
4.5V
t
R
MT5C2568 / AS5C2568
Rev. 4.5 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
432
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V
IH
V
IL
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DON’T CARE
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