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AS5C2568C-35L/883C 参数 Datasheet PDF下载

AS5C2568C-35L/883C图片预览
型号: AS5C2568C-35L/883C
PDF下载: 下载PDF文件 查看货源
内容描述: 32K ×8 SRAM SRAM存储器阵列 [32K x 8 SRAM SRAM MEMORY ARRAY]
分类和应用: 存储静态存储器
文件页数/大小: 16 页 / 141 K
品牌: AUSTIN [ AUSTIN SEMICONDUCTOR ]
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SRAM  
MT5C2568  
AS5C2568  
+5V  
Austin Semiconductor, Inc.  
+5V  
ACTEST CONDITIONS  
Input pulse levels....................................................Vss to 3V  
Input rise and fall times.....................................................5ns  
Input timing reference level.............................................1.5V  
Output reference level......................................................1.5V  
Output load.................................................See figures 1 & 2  
480  
480  
Q
Q
30 pF  
255  
5 pF  
255  
Fig. 1  
Fig. 2  
OUTPUT LOAD  
EQUIVALENT  
OUTPUT LOAD  
EQUIVALENT  
NOTES  
7. At any given temperature and voltage condition, tHZCE  
1. All voltages referenced to VSS (GND).  
2. -3V for pulse width < 20ns  
is less thantLZCE, and HZWE is less than tLZWE.  
t
3. ICC is dependent on output loading and cycle rates. The  
specified value applies with the outputs unloaded, and  
8. WE\ is HIGH for READ cycle.  
9. Device is continuously selected. Chip enables and  
output enables are held in their active state.  
10. Address valid prior to, or coincident with, latest  
occurring chip enable.  
f =  
1
Hz.  
tRC (MIN)  
4. This parameter is guaranteed but not tested.  
5. Test conditions as specified with the output loading as  
shown in Fig. 1 unless otherwise noted.  
6. t HZCE, tHZOE and tHZWE are specified with CL = 5pF  
as in Fig. 2. Transition is measured ±500mV typical from  
steady state voltage, allowing for actual tester RC time  
constant.  
t
11. RC = Read Cycle Time.  
12. Chip enable (CE\) and write enable (WE\) can initiate and  
terminate a WRITE cycle.  
DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only)  
DESCRIPTION  
CONDITIONS  
SYM  
MIN  
MAX  
UNITS  
NOTES  
2
V
VCC for Retention Data  
VDR  
CE\ > (VCC-0.2V)  
Data Retention Current  
ICCDR  
1
mA  
VIN > (VCC-0.2V)  
or < 0.2V  
Chip Deselect to Data  
Retention Time  
tCDR  
tR  
0
--  
ns  
ns  
4
Operation Recovery Time  
4, 11  
tRC  
LOW Vcc DATA RETENTION WAVEFORM  
DATA RETENTION MODE  
VCC  
4.5V  
4.5V  
VDR > 2V  
t
tCDR  
R
VIH  
VIL  
VDR  
CE\  
DON’T CARE  
UNDEFINED  
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.  
MT5C2568 / AS5C2568  
Rev. 4.5 06/05  
5
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