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AS58LC1001F-25/XT 参数 Datasheet PDF下载

AS58LC1001F-25/XT图片预览
型号: AS58LC1001F-25/XT
PDF下载: 下载PDF文件 查看货源
内容描述: 128K ×8 EEPROM耐辐射 [128K x 8 EEPROM Radiation Tolerant]
分类和应用: 内存集成电路可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件页数/大小: 21 页 / 272 K
品牌: AUSTIN [ AUSTIN SEMICONDUCTOR ]
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EEPROM
Austin Semiconductor, Inc.
FUNCTIONAL DESCRIPTION
AUTOMATIC PAGE WRITE
The Page Write feature allows 1 to 128 Bytes of data to be
written into the EEPROM in a single cycle and allows the un-
defined data within 128 Bytes to be written corresponding to
the undefined address (A
0
to A
6
). Loading the first Byte of
data, the data load window of 30μs opens for the second. In the
same manner each additional Byte of data can be loaded within
30μs. In case CE\ and WE\ are kept high for 100μs after data
input, the EEPROM enters erase and write automatically and
only the input data can be written into the EEPROM. In Page
mode the data can be written and accessed 10
4
times per page,
and in Byte mode 10
3
times per Byte.
AS58LC1001
DATA PROTECTION
To protect the data during operation and power on/off, the
AS58C1001 has:
1. Data protection against Noise on Control Pins (CE\, OE\,
WE\) during Operation. During readout or standby, noise on
the control pins may act as a trigger and turn the EEPROM to
programming mode by mistake. To prevent this phenomenon,
the AS58LC1001 has a noise cancellation function that cuts
noise if its width is 20ns or less in programming mode. Be
careful not to allow noise of a width of more than 20ns on the
control pins.
DATA\ POLLING
Data\ Polling allows the status of the EEPROM to be deter-
mined. If the EEPROM is set to Read mode during a Write
cycle, and inversion of the last Byte of data to be loaded out-
puts from I/O, to indicate that the EEPROM is performing a
Write operation.
WRITE PROTECTION
(1) Noise protection: Noise on a write cycle will not act as
a trigger with a WE\ pulse of less than 20ns.
(2) Write inhibit: Holding OE\ low, WE\ high or CE\ high,
inhibits a write cycle during power on/off.
WE\ AND CE\ PIN OPERATION
During a write cycle, addresses are latched by the falling
edge of WE\ or CE\, and data is latched by the rising edge of
WE\ or CE\.
WRITE/ERASE ENDURANCE AND
DATA RETENTION
The endurance with page programming is 10
4
cycles (1%
cumulative failure rate) and the data retention time is more than
10 years when a device is programmed less than 10
4
cycles.
AS58LC1001
Rev. 1.0 12/08
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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