SDRAM
Austin Semiconductor, Inc.
CAS Latency
The CAS latency is the delay, in clock cycles, between
the registration of a READ command and the availability of the
first piece of output data. The latency can be set to two or three
clocks.
If a READ command is registered at clock edge n, and
the latency is m clocks, the data will be available by clock edge
n+m. The DQs will start driving as a result of the clock edge one
cycle earlier (n + m - 1), and provided that the relevant access
times are met, the data will be valid by clock edge n + m. For
example, assuming that the clock cycle time is such that all
relevant access times are met, if a READ command is registered
at T0 and the latency is programmed to two clocks, the DQs will
start driving after T1 and the data will be valid by T2, as shown
in Figure 2. Table 2 below indicates the operating frequencies at
which each CAS latency setting can be used.
AS4SD4M16
Reserved states should not be used as unknown op-
eration or incompatibility with future versions may result.
Operating Mode
The normal operating mode is selected by setting
M7and M8 to zero; the other combinations of values for M7
and M8 are reserved for future use and/or test modes. The
programmed burst length applies to both READ and WRITE
bursts.
Test modes and reserved states should not be used
because unknown operation or incompatibility with future ver-
sions may result.
Write Burst Mode
When M9 = 0, the burst length programmed via M0-
M2 applies to both READ and WRITE bursts; when M9 = 1,
the programmed burst length applies to READ bursts, but write
accesses are single-location (nonburst) accesses.
T0
CLK
T1
321
321
321
321
321
321
321
321
T2
321
321
321
321
T3
Table 2
CAS LATENCY
ALLOWABLE OPERATING FREQUENCY
(MHz)
SPEED CAS LATENCY = 2
CAS LATENCY = 3
COMMAMD
DQ
D
OUT
t
AC
CAS Latency = 2
T0
CLK
T1
T2
COMMAMD
READ
NOP
NOP
t
LZ
NOP
t
OH
D
OUT
DQ
t
AC
CAS Latency = 3
UNDEFINED
DON’T CARE
Figure 2
CAS LATENCY
AS4SD4M16
Rev. 2.1 6/05
8
4321
4321
4321
4321
4321
321
321
321
321
321
321
321
321
321
321
31132
342
243
331121
12111
2221
311121
1122
3231
242
332111
2231
311121
342
243
321
321
321
321
321
321
321
321
311
2
32321
2311
3211
12
2131
33211
122
331
222
2
2232
31211
1
22211
33321
1
321
321
321
321
321
321
321
321
54321
21
21
54321
21
54321
21
54321
3211
32
21
3211
21
32
3321
21
32
3211
21
READ
NOP
t
LZ
NOP
t
OH
-8
-10
≤ 83
≤ 66
≤
125
≤
100
T3
T4
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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