SDRAM
Austin Semiconductor, Inc.
FUNCTIONAL DESCRIPTION
In general, the 64Mb SDRAM is quad-bank DRAM (1
Meg x 16 x 4 banks) which operate at 3.3V and include a
synchronous interface (all signals are registered on the
positive edge of the clock signal, CLK). Each of the x16’s
16,777,216-bit banks is organized as 4,096 rows by 256 columns
by 16 bits.
Read and write accesses to the SDRAM are burst
oriented; accesses start at a selected location and continue for
a programmed number of locations in a programmed sequence.
Accesses begin with the registration of an ACTIVE command
which is then followed by a READ or WRITE command. The
address bits registered coincident with the ACTIVE command
are used to select the bank and row to be accessed (BA0 and
BA1 select the bank, A0-A11 select the row). The address bits
( x16: A0-A7) registered coincident with the READ or WRITE
command are used to select the starting column location for the
burst access.
Prior to normal operation, the SDRAM must be initial-
ized. The following sections provide detailed information
covering device initialization, register definition, command
descriptions and device operation.
Initalization
SDRAMs must be powered up and initialized in a
predefined manner. Operational procedures other than those
specified may result in undefined operation. Once power is
applied to V
DD
and V
DD
Q (simultaneously) and the clock is
stable, the SDRAM requires a 100µs delay prior to applying an
executable command. Starting at some point during this 100µs
period and continuing at least through the end of this period,
COMMAND INHIBIT or NOP commands should be applied.
Once the 100µs delay has been satisfied with at least
one COMMAND INHIBIT or NOP command having been ap-
plied, a PRECHARGE command should be applied. All banks
must be precharged, thereby placing the device in the all banks
idle state.
Once in the idle state, two AUTO REFRESH cycles
must be performed. After the AUTO REFRESH cycles are
complete, the SDRAM is ready for Mode Register program-
ming. Because the Mode Register will power up in an unknown
state, it should be loaded prior to applying any operational
command.
AS4SD4M16
REGISTER DEFINITION
Mode Register
The Mode Register is used to define the specific mode
of operation of the SDRAM. This definition includes the
selection of a burst length, a burst type, a CAS latency, an
operating mode and a write burst mode, as shown in Figure 1.
The Mode Register is programmed via the LOAD MODE
REGISTER command and will retain the stored information until
it is programmed again or the device loses power.
Mode register bits M0-M2 specify the burst length,
M3 specifies the type of burst (sequential or interleaved), M4-
M6 specify the CAS latency, M7 and M8 specify the operating
mode, M9 specifies the WRITE burst mode, and M10 and M11
are reserved for future use.
The Mode Register must be loaded when all banks are
idle, and the controller must wait the specified time before
initiating the subsequent operation. Violating either of these
requirements will result in unspecified operation.
Burst Length
Read and write accesses to the SDRAM are burst
oriented, with the burst length being programmable, as shown
in Figure 1. The burst length determines the maximum number
of column locations that can be accessed for a given READ or
WRITE command. Burst lengths of 1, 2, 4, or 8 locations are
available for both the sequential and the interleaved burst types,
and a full-page burst is available for the sequential type. The
full-page burst is used in conjunction with the BURST
TERMINATE command to generate arbitrary burst lengths.
Reserved states should not be used, as unknown
operation or incompatibility with future versions may result.
When a READ or WRITE command is issued, a block
of columns equal to the burst length is effectively selected. All
accesses for that burst take place within this block, meaning
that the burst will wrap within the block if a boundary is reached.
The block is uniquely selected by A1-A7 (x16) when the burst
length is set to two; A2-A7 (x16) when the burst length is set to
four; and by A3-A7 (x16) when the burst length is set to eight.
The remaining (least significant) address bit(s) is (are) used to
select the starting location within the block. Full-page bursts
wrap within the page if the boundary is reached.
AS4SD4M16
Rev. 2.1 6/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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AUSTIN [ AUSTIN SEMICONDUCTOR ]
