SDRAM
AS4SD4M16
Austin Semiconductor, Inc.
OPERATION
BANK/ROW ACTIVATION
Before any READ or WRITE commands can be issued
to a bank within the SDRAM, a row in that bank must be
“opened.” This is accomplished via the ACTIVE command,
which selects both the bank and the row to be activated.
After opening a row (issuing an ACTIVE command), a
CLK
HIGH
CKE
CS\
READ or WRITE command may be issued to that row, subject
to the tRCD specification. tRCD (MIN) should be divided by the
clock period and rounded up to the next whole number to deter-
mine the earliest clock edge after the ACTIVE command on
which a READ or WRITE command can be entered. For
RAS\
CAS\
WE\
example, a tRCD specification of 30ns with a 90 MHz clock
(11.11ns period) results in 2.7 clocks, rounded to 3. This is
reflected in Figure 4, which covers any case where 2 < tRCD
(MIN)/ tCK ≤ 3. (The same procedure is used to convert other
specification limits from time units to clock cycles).
ROW ADDRESS
A0-A11
BA0, 1
BANK ADDRESS
A subsequent ACTIVE command to a different row in
the same bank can only be issued after the previous active row
has been “closed” (precharged). The minimum time interval
between successive ACTIVE commands to the same bank is
Figure 3
ACTIVATING A SPECIFIC ROW IN A
SPECIFIC BANK
defined by tRC.
A subsequent ACTIVE command to another bank can
be issued while the first bank is being accessed, which results
in a reduction of total row-access overhead. The minimum time
interval between successive ACTIVE commands to different
banks is defined by tRRD
.
T0
T2
T4
T1
T3
CLK
READ or
WRITE
COMMAND
ACTIVE
NOP
NOP
tRCD
DON’T CARE
Figure 4
EXAMPLE: MEETING tRCD (MIN)WHEN 2<tRCD (MIN)/tCK<3
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS4SD4M16
Rev. 1.5 10/01
12
AUSTIN [ AUSTIN SEMICONDUCTOR ]
