SDRAM
Austin Semiconductor, Inc.
WRITE (continued)
selects the bank, and the address provided on inputs A0-A8
selects the starting column location. The value on input A10
determines whether or not auto precharge is used. If auto
precharge is selected, the row being accessed will be precharged
at the end of the WRITE burst; if auto precharge is not
selected, the row will remain open for subsequent accesses.
Input data appearing on the DQs is written to the memory array
subject to the DQM input logic level appearing coincident with
the data. If a given DQM signal is registered LOW, the
corresponding data will be written to memory; if the DQM
signal is registered HIGH, the corresponding data inputs will be
ignored, and a WRITE will not be executed to that byte/column
location.
PRECHARGE
The PRECHARGE command is used to deactivate the open
row in a particular bank or the open row in all banks. The
bank(s) will be available for a subsequent row access a speci-
fied time (t
RP
) after the PRECHARGE command is issued. Input
A10 determines whether one or all banks are to be precharged,
an in the case where only one bank is to be precharged, inputs
BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as
“Don’t Care.” Once a bank has been precharged, it is in the idle
state and must be activated prior to any READ or WRITE com-
mands being issued to that bank.
AUTO PRECHARGE
Auto precharge is a feature which performs the same
individual-bank PRECHARGE functions described above,
without requiring an explicit command. This is accomplished
by using A10 to enable auto precharge in conjunction with a
specific READ or WRITE command. A PRECHARGE of the
bank/row that is addressed with the READ or WRITE
command is automatically performed upon completion of the
READ or WRITE burst, except in the full-page burst mode,
where AUTO PRECHARGE does not apply. Auto precharge is
nonpersistent in that it is either enabled or disabled for each
individual READ or WRITE command.
Auto precharge ensures that the precharge is initiated at
the earliest valid stage within a burst. The user must not issue
another command to the same bank until the precharge time
(t
RP
) is completed. This is determined as if an explicit
PRECHARGE command was issued at the earliest possible time,
as described for each burst type in the Operation section of this
data sheet.
BURST TERMINATE
The BURST TERMINATE command is used to truncate
either fixed-length or full-page bursts. The most recently
AS4SD32M16
Rev. 1.1 3/08
AS4SD32M16
registered READ or WRITE command prior to the BURST
TERMINATE command will be truncated, as shown in the
Operation section of this data sheet.
AUTO REFRESH (IT & IT+ Temp options ONLY)
AUTO REFRESH is used during normal operation of the
SDRAM and is analogous to CAS\-BEFORE-RAS\ (CBR)
REFRESH in conventional DRAMs. This command is
nonpersistent, so it must be issued each time a refresh is
required. All active banks must be precharged prior to issuing
an AUTO REFRESH command. The AUTO REFRESH
command should not be issued until the minimum t
RP
has been
met after the PRECHARGE command as shown in the
Operations section.
The addressing is generated by the internal refresh
controller. This makes the address bits “Don’t Care” during an
AUTO REFRESH command. The 512Mb SDRAM requires 8,192
AUTO REFRESH cycles every 64ms (t
REF
), regardless of width
operation. Providing a distributed AUTO REFRESH command
every 7.81µs will meet the refresh requirement and ensure that
each row is refreshed. Alternatively, 8,192 AUTO REFRESH
commands can be issued in a burst at the minimum cycle rate
(t
RFC
), once every 64ms.
SELF REFRESH (IT & IT+ Temp options ONLY)
The SELF REFRESH command can be used to retain data
in the SDRAM, even if the rest of the system is powered down.
When in the self refresh mode, the SDRAM retains data
without external clocking. The SELF REFRESH command is
initiated like and AUTO REFRESH command except CKE is
disabled (LOW). Once the SELF REFRESH command is
registered, all the inputs to the SDRAM become “Don’t Care”
with the exception of CKE, which must remain LOW.
Once self refresh mode is engaged, the SDRAM provides
its own internal clocking, causing it to perform its own AUTO
REFRESH cycles. The SDRAM must remain in self refresh
mode for a minimum period equal to tRAS and may remain in
self refresh mode for an indefinite period beyond that.
The procedure for exiting self refresh requires a sequence
of commands. First, CLK must be stable (stable clock is defined
as a signal cycling within timing constraints specified for the
clock pin) prior to CKE going back HIGH. Once CKE is HIGH,
the SDRAM must have NOP commands issued (a minimum of
two clocks) for tXSR because time is required for the
completion of any internal refresh in progress.
Upon exiting the self refresh mode, AUTO REFRESH
commands must be issued every 7.81µs or less as both SELF
REFRESH and AUTO REFRESH utilize the row refresh counter.
The SELF REFRESH and AUTO REFRESH option are available
with the IT and IT+ temperature options. They are not
available with the XT temperature options.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
8
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