SDRAM
Austin Semiconductor, Inc.
PIN DESCRIPTIONS
PIN NUMBER
68
SYMBOL
CLK
TYPE
DESCRIPTION
Clock: CLK is driven by the system clock. All SDRAM input
signals are sampled on the positive edge of CLK. CLK also
Input
increments the internal burst counter and controls the output
registers.
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the
CLK signal. Deactivating the clock provides PRECHARGE
POWER-DOWN and SLEF REFRESH operation (all banks idle),
ACTIVE POWER-DOWN (row active in any bank) or CLOCK
SUSPEND operation (burst/access in progress). CKE is
Input
synchronous except after the device enters power-down and self
refresh modes, where CKE becomes asynchronous until after
exiting the same mode. The input buffers, including CLK, are
disabled during power-down and self refresh modes, providing low
standby power. CKE may be tied HIGH.
Chip Select: CS\ enables (registered LOW) and disables
(registered HIGH) the command decoder. All commands are
masked when CS\ is registered HIGH. CS\ provides for external
bank selection on systems with multiple banks. CS\ in considered
part of the command code.
Command Inputs: WE\, CAS\ and RAS\ (along with CS\) define
the command being entered.
Input/Output Mask: DQM is an input mask signal for write
accesses and an output enable signal for read accesses. Input
data is masked when DWM is sampled HIGH during a WRITE
cycle. The outptu buffers are placed in a High-Z state (two-clock
latency) when DQM is sampled HIGH during a READ cycle.
DQM0 corresponds to DQ0-7, DQM2 to DQ16-23, DQM3 to
DQ24-31
Bank Address Inputs: BA0 and BA1 define to which bank the
ACTIVE, READ, WRITE, or PRECHARGE command is being
applied.
AS4SD2M32
67
CKE
20
CS\
Input
17, 18, 19
WE\, CAS\,
RAS\
Input
16,71,28,59
DQM0, DQM1,
DQM2, DQM3
Input
22, 23
BA0, BA1
Input
25, 26, 27, 60, 61, 62, 63, 64,
65, 66, 24
A0 - A10
Address Inputs: A0-A12 are sampled during the ACTIVE
command (row address A0-A12) and READ/WRITE command
(column-address A0-A8; with A10 defining auto precharge) to
select one location out of the memory array in the respective
Input
bank. A10 is sampled during a PRECHARGE command to
determine if all banks are to be prechaged (A10 [HIGH]) or bank
selected by (A10 [LOW]). The address inputs also provide the
op-code during LOAD MODE REGISTER COMMAND.
2,4,5,7,8,10,11,13,74,76,77,
79,80,82,83,85,31,33,34,36,3
7,39,40,42,45,47,48,50,51,53
,54,56
14, 21, 30, 57, 69, 70, 73
3,9,35,41,49,55,75,81
6,12,32,38,46,52,78,84
1,15,29,43
44,58,72,86
AS4SD2M32
Rev. 1.0 1/08
DQ0 - DQ31
I/O
Data Input/Output: Data bus
NC
V
DD
Q
V
SS
Q
V
DD
V
SS
No Connect: These pins should be left unconnected.
DQ Power: Isolated DQ power to the die for improved noise
Supply
immunity.
DQ Ground: Isolated DQ ground to the die for imporved noise
Supply
immunity.
Supply Power Supply: +3.3V ±0.3V
Supply Ground
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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AUSTIN [ AUSTIN SEMICONDUCTOR ]
