SDRAM
AS4SD2M32
Austin Semiconductor, Inc.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING
CONDITIONS5,6,8,9,11
-6
-7
-75
PARAMETER
SYM
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
NOTES
tAC(3)
5.5
5.5
5.4
ns
27
CL = 3
CL = 2
Access time from CLK (pos. edge)
tAC(2)
tAH
7.5
8
8
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
Address hold time
Address setup time
CLK high-level width
CLK low-level width
0.8
1.5
2
0.8
1.5
2.5
2.5
7
0.8
1.5
2.5
2.5
7.5
10
tAS
tCH
tCL
2
tCK(3)
tCK(2)
tCKH
tCKS
tCMH
tCMS
tDH
6
23
23
CL = 3
CL = 2
Clock cycle time
10
0.8
1
10
0.8
1
CKE hold time
0.8
1.5
0.8
1.5
0.8
1.5
CKE setup time
CS\, RAS\, CAS\, WE\, DQM hold time
CS\, RAS\, CAS\, WE\, DQM setup time
Data-in hold time
0.8
1.5
0.8
1.5
0.8
1.5
0.8
1.5
Data-in setup time
tDS
tHZ(3)
tHZ(2)
tLZ
5.5
7.5
5.5
8
5.5
8
10
10
CL = 3
CL = 2
Data-out high-impedance time
Data-out low-impedance time
Data-out hold time (load)
0
2
0
2.5
1.5
37.5
63
0
3
tOH
Data-out hold time (no load)
ACTIVE to PRECHARGE command
ACTIVE to ACTIVE command
ACTIVE to READ or WRITE delay
Refresh period (4,092 rows)
AUTO REFRESH period
tOH
1.3
37.5
60
1.8
37.5
70
28
N
tRAS
tRC
120K
64/16
120K
64/16
120K
tRCD
tREF
tRFC
tRP
18
20
20
64 / 16
34
35
60
18
12
0.3
70
20
14
0.3
70
20
15
0.3
PRECHARGE command period
ACTIVE bank a to ACTIVE bank b command
Transition time
tRRD
tT
1.2
1.2
1.2
7
1 CLK +
6ns
1 CLK +
7ns
1 CLK +
7.5ns
15
ns
24
WRITE recovery time
tWR
ns
ns
25
Exit SELF REFRESH to ACTIVE command
tXSR
70
70
75
20, 35
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS4SD2M32
Rev. 1.0 1/08
29
AUSTIN [ AUSTIN SEMICONDUCTOR ]
