SDRAM
Austin Semiconductor, Inc.
GENERAL DESCRIPTION
The 64Mb SDRAM is a high-speed CMOS, dynamic ran-
dom-access memory containing 67,108,864 bits. It is internally
configured as a quad-bank DRAM with a synchronous inter-
face (all signals are registered on the positive edge of the clock
signal, CLK). Each of the 16,777,216-bit banks is organized as
2,048 rows by 256 columns by 32 bits.
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for a pro-
grammed number of locations in a programmed sequence. Ac-
cesses begin with the registration of an ACTIVE command,
which is then followed by a READ or WRITE command. The
address bits registered coincident with the ACTIVE command
are used to select the bank and row to be accessed (BA0, BA1
select the bank; A0-A10 select the row). The address bits reg-
istered coincident with the READ or WRITE command are used
to select the starting column location for the burst access.
The SDRAM provides for programmable READ or WRITE
burst lengths of 1, 2, 4, or 8 locations, or the full page, with a
burst terminate option. An auto precharge function may be
enabled to provide a self-timed row precharge that is initiated at
the end of the burst sequence.
The 64Mb SDRAM uses an internal pipelined architecture
to achieve high-speed operation. This architecture is compat-
ible with the 2n rule of prefetch architectures, but it also allows
the column address to be changed on every clock cycle to
achieve a high-speed, fully random operation. Precharging one
bank while accessing one of the other three banks will hide the
precharge cycles and provide seamless, high-speed, random-
access operation.
The 64Mb SDRAM is designed to operate in 3.3V memory
systems. An auto refresh mode is provided, along with a power-
saving, power-down mode. All inputs and outputs are LVTTL-
compatible.
SDRAMs offer substantial advances in DRAM operating
performance, including the ability to synchronously burst data
at a high data rate with automatic column-address generation,
the ability to interleave between internal banks to hide precharge
time and the capability to randomly change column addresses
on each clock cycle during a burst access.
AS4SD2M32
FUNCTIONAL BLOCK DIAGRAM
CLK
CKE
CS
RAS
CAS
WE
DQM0-3
COMMAND
DECODER
&
CLOCK
GENERATOR
DATA IN
BUFFER
32
32
MODE
REGISTER
11
REFRESH
CONTROLLER
DQ 0-31
SELF
REFRESH
CONTROLLER
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
BA0
BA1
11
DATA OUT
BUFFER
32
32
V
DD
/V
DDQ
GND/GNDQ
REFRESH
COUNTER
2048
2048
2048
2048
ROW
DECODER
MULTIPLEXER
MEMORY
CELL
ARRAY
11
ROW
ADDRESS
LATCH
11
ROW
ADDRESS
BUFFER
BANK 0
SENSE AMP
I/O GATE
COLUMN
ADDRESS
LATCH
256
(x
32)
BANK CONTROL LOGIC
BURST COUNTER
COLUMN DECODER
COLUMN
ADDRESS
BUFFER
AS4SD2M32
Rev. 1.0 1/08
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
2
AUSTIN [ AUSTIN SEMICONDUCTOR ]
