AS4SD16M72PBG-s/IT,ET,XT
16M x 72, SDR SDRAM, 3.3v Core/ 3.3v IO
Auto Refresh
AUTO REFRESH is used during normal operation of the
SDRAM MCP and is analogous to CAS\-BEFORE-RAS\
(CBR) REFRESH in conventional DRAMs. This command is
non-persistent, so it must be issued each time a refresh is
required. All active banks must be PRECHARGED prior to
issuing an AUTO REFRESH command. The AUTO
REFRESH command should not be issued until the minimum
tRP has been met after the PRECHARGE command.
The addressing is generated by the internal REFRESH
controller. This makes the address bits “Don’t Care” during
an AUTO REFRESH command. The 256Mb SDRAM MCP
requires 8,192 AUTO REFRESH cycles every 64ms (tREF).
Providing a distributed AUTO REFRESH command every
7.81us will meet the refresh requirement and ensure that each
row is refreshed. Alternatively, 8,192 AUTO REFRESH
commands can be issued in a burst at the minimum cycle rate
(tRFC), once every 64ms.
Upon exiting the SELF REFRESH mode, AUTO
REFRESH commands must be issued every 7.81us or less
as both SELF REFRESH and AUTO REFRESH utilize
the row refresh counter.
Self Refresh
The SELF REFRESH command can be used to retain data in
the SDRAM MCP, even if the rest of the system is powered
down. When in the self refresh mode, the SDRAM MCP
retains data without external clocking. The SELF REFRESH
command is initiated like an AUTO REFRESH command
except CKE is disabled (LOW). Once the SELF REFRESH
command is registered, all the inputs to the SDRAM MCP
become “Don’t Care” with the exception of CKE, which must
remain LOW.
Once self refresh mode is engaged, the SDRAM provides its
own internal clocking, causing it to perform its own AUTO
REFRESH cycles. The SDRAM MCP must remain in SELF
REFRESH mode for a minimum period equal to tRAS and
may remain in SELF REFRESH for an indefinite period of
time beyond the minimum.
The procedure for exiting SELF REFRESH requires a
sequence of commands. First, CLK must be stable (stable
clock is defined as a signal cycling within timing constraints
specified for the clock pin) prior to CKE going back HIGH.
Once CKE is HIGH, the SDRAM MCP must have NOP
commands issued (a minimum of two clocks) for tXSR
because time is required for the completion of any internal
REFRESH in progress.
Austin Semiconductor, Inc.
Proprietary Material
ASI Product Marketing
AUSTIN [ AUSTIN SEMICONDUCTOR ]
