AS4SD16M72PBG-s/IT,ET,XT
16M x 72, SDR SDRAM, 3.3v Core/ 3.3v IO
Features
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Performance: 100MHz, 125MHz and 133MHz
Core Supply Voltage = 3.3v +/- 0.3v
IO Supply Voltage = 3.3v +/- 0.3v
Internal, pipeline, architecture
Single Clock Input
Positive edge; Command execution
DLL for alignment of DQ and DQS transitions
Four internal banks for concurrent operation
Data Mask (DM) for masking write data
Programmable IOL/IOH
Programmable Burst length: 1,2,4,8 or full page
Auto Precharge
Self Refresh Mode on /IT and /ET devices
This architecture is compatible with the 2n rule of
PREFETCH architectures, but it also allows the column
address to be changed on every clock cycle to achieve a
high-speed, fully random access. PRECHARGING one
bank while accessing one of the other three banks will
hide the precharge cycles and provide seamless array
access at rated speed.
Initialization
Austin Semiconductor’s AS4SD16M72PBG is like all
other SDRAM devices and for correct functional
operation must be properly initialized in a predefined
manor, following the allowable functional modes.
Operation of the device outside of the prescribed modes
may result in undefined device operation. Once power is
applied to VDD and VDDQ and the clock is stable, the
device requires a 100us delay prior to issuing a command
other than a COMMAND INHIBIT or NOP. Starting at
some point during this 100us period and continuing at
least through the end of this period, COMMAND
INHIBIT or NOP commands should be applied.
Once the 100us delay has been satisfied with at least one
COMMAND INHIBIT or NOP, a PRECHARGE
command should be applied. All banks must then be
PRECHARGED, thereby placing the device in the all
banks idle state.
Once in the idle state, two AUTO REFRESH cycles must
be performed. After the AUTO REFRESH cycles are
complete, the SDRAM is ready for mode register
programming. Because the mode register will power up
in an unknown state, it should be loaded prior to applying
any operational command.
Silicon Base:
•Micron: Die equivalency to MT48LC16M16A2
General Description
Austin Semiconductor’s 1.2Gb, Synchronous DRAM is a high
speed CMOS MCP and is packaged in a 25mm x 32mm, 219
PBGA with a ball pitch of 1.27mm. This device contains (5)
x16 synchronous dynamic random access die, each containing
a total density of 268,435,456 bits. The end organization of
the MCP is 16M x 80.
Read and Write accesses to the array are burst oriented;
accesses start at a selected location and continue for a
programmed number of locations, as prescribed by the
programmed sequence. Accesses begin with the registration
of an ACTIVE command, which is then followed by a READ
or WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank and
row to be accessed (BA0, BA1 select the bank; A0-A12 select
the row). The address bits registered at the initiation of
READ or WRITE are used to select the starting column
location for the burst access.
The SDRAM provides for programmable READ or WRITE
burst lengths of 1, 2, 4, 8 or full page, with a burst terminate
option. An AUTO PRECHARGE function may be enabled to
provide a self-timed row precharge that is initiated at the end
of the burst sequence.
Austin Semiconductor’s AS4SD16M72PBG device uses an
internal pipeline architecture to achieve high speed operation.
Austin Semiconductor, Inc.
Register Definition [MODE REGISTER]
The mode register is used to define the specific mode of
operation of the SDRAM MCP. This definition includes
the selection of a burst length, a burst type, a CAS
latency, an operating mode and a WRITE burst mode.
The MODE REGISTER is programmed via the LOAD
MODE REGISTER command and will retain the stored
information until it is programmed again or the device
loses power.
Mode register bits M0-M2 specify the burst length, M3
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