SDRAM
AS4SD16M16
Austin Semiconductor, Inc.
ALTERNATING BANK WRITE ACCESSES1
TIMING PARAMETERS
-75
-75
SYMBOL*
MIN
MAX
UNITS
SYMBOL*
MIN
MAX
UNITS
t
0.8
ns
t
ns
AH
CMS
1.5
t
1.5
2.5
2.5
7.5
10
ns
ns
ns
ns
ns
ns
ns
ns
t
t
ns
ns
ns
ns
ns
ns
ns
ns
AS
CH
DH
DS
0.8
1.5
t
t
t
44
66
80,000
CL
RAS
t
t
t
RC
CK(3)
CK(2)
t
t
20
RCD
t
0.8
1.5
0.8
t
20
CKH
RP
RRD
t
15
CKS
t
t
Note 2
CMH
WR
*CAS latency indicated in parentheses.
NOTES:
1. For this example, the burst length = 4.
2. Requires one clock plus time (7.5ns) with auto precharge or 14ns to 15ns with PRECHARGE.
3. A9, A11, and A12 = “Don’t Care”
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS4SD16M16
Rev. 1.0 11/02
47
AUSTIN [ AUSTIN SEMICONDUCTOR ]
