SDRAM
AS4SD16M16
Austin Semiconductor, Inc.
ALTERNATING BANK READ ACCESSES1
TIMING PARAMETERS
-75
-75
SYMBOL*
MIN
MAX
5.4
6
UNITS
SYMBOL*
MIN
MAX
UNITS
t
ns
t
ns
AC(3)
AC(2)
CMH
0.8
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
ns
ns
ns
ns
ns
ns
ns
ns
CMS
1.5
1
t
0.8
1.5
2.5
2.5
7.5
10
t
LZ
AH
t
t
3
AS
CH
OH
t
t
44
66
20
20
15
80,000
RAS
t
t
RC
CL
t
t
t
CK(3)
CK(2)
RCD
t
RP
RRD
t
0.8
1.5
t
CKH
t
CKS
*CAS latency indicated in parentheses.
NOTES:
1. For this example, the burst length = 4, the CAS latency = 2.
2. A9, A11, and A12 = “Don’t Care”
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS4SD16M16
Rev. 1.0 11/02
40