SDRAM
AS4SD16M16
Austin Semiconductor, Inc.
WRITE with Auto Precharge
4. Interrupted by a WRITE (with or without auto precharge): A
3. Interrupted by a READ (with or without auto precharge); A WRITE to bank m will interrupt a WRITE on bank n when
READ to bank m will interrupt a WRITE on bank n when
registered, with the data-out appearing CAS latency later. The
registered. The PRECHARGE to bank n will begin after tWR is
met, where tWR begins when the WRITE to bank m is registered.
The last valid data WRITE to bank n will be data registered one
clock prior to the WRITE to bank m (Figure 26).
PRECHARGE to bank n will begin after tWR is met, where tWR
begins when the READ to bank m is registered. The last valid
WRITE to bank n will be data-in registered one clock prior to
the READ to bank m (Figure 26).
FIGURE 26: WRITE With Auto Precharge Interrupted by a READ
FIGURE 27: WRITE With Auto Precharge Interrupted by a WRITE
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS4SD16M16
Rev. 1.0 11/02
21
AUSTIN [ AUSTIN SEMICONDUCTOR ]
