SDRAM
AS4SD16M16
Austin Semiconductor, Inc.
WRITEs
WRITE bursts are initiated with a WRITE command, as
shown in Figure 13.
Data for any WRITE burst may be truncated with a
subsequent WRITE command, and data for a fixed-length
WRITE burst may be immediately followed by data for a WRITE
command. The new WRITE command can be issued on any
clock following the previous WRITE command, and the data
provided coincident with the new command applies to the new
command. An example is shown in Figure 15. Data n+1 is either
the last of a burst of two or the last desired of a longer burst.
The 256MB SDRAM uses a pipelined architecture and
therefore does not require the 2n rule associated with a prefetch
architecture. A WRITE command can be initiated on any clock
cycle following a previous WRITE command. Full-speed ran-
dom write accesses within a page can be performed to the same
bank, as shown in Figure 16, or each subsequent WRITE may
be preformed to a different bank.
The starting column and blank addresses are provided with
the WRITE command, an auto precharge is either enabled or
disabled for that access. If auto precharge is enabled, the row
being accessed is precharged at the completion of the burst.
For the generic WRITE commands used in the following
illustrations, auto precharge is disabled.
During WRITE bursts, the first valid data-in element will
be registered coincident with the WRITE command.
Subsequent data elements will be registered on each
successive positive clock edge. Upon completion of a fixed-
length burst, assuming no other commands have been
initiated, the DQs will be ignored (see Figure 14). A full-page
burst will continue until terminated. (At the end of the page, it
will wrap to the start address and continue.)
FIGURE 14: WRITE Burst
FIGURE 13: WRITE Command
FIGURE 15: WRITE to WRITE
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS4SD16M16
Rev. 1.0 11/02
16
AUSTIN [ AUSTIN SEMICONDUCTOR ]
