16 Meg FPM DRAM
AS4LC4M4
Austin Semiconductor, Inc.
TEST MODE CYCLE11
-60
-70
SYMBOL
PARAMETER
MIN
MAX
MIN
MAX
UNITS
NOTES
Random read or write cycle time
Read-modify-write cycle time
Access time from RAS\
Access time from CAS\
Access time from column address
RAS\ pulse width
115
ns
tRC
160
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRWC
tRAC
tCAC
tAA
65
20
3, 4, 10, 12
3, 4, 5, 12
3, 10 ,12
35
65
20
20
65
35
45
90
60
65
45
90
65
10K
10K
tRAS
tCAS
tRSH
tCSH
tRAL
CAS\ pulse width
RAS\ hold time
CAS\ hold time
Column address to RAS\ lead time
CAS\ to W\ delay time
7
7
7
tCWD
tRWD
tAWD
tCPWD
tPC
RAS\ to W\ delay time
Column address to W\ delay time
CAS\ precharge to W\ delay time
Fast Page cycle time
Fast Page read-modify-write time
RAS\ pulse width (Fast Page Cycle)
Access time from CAS\ precharge
OE\ access time
tPRWC
tRASP
tCPA
tOEA
tOED
tOEH
200K
40
3
20
OE\ to data delay
20
20
OE\ command hold time
NOTES:
1. An initial pause of 200us is required after power-up followed by an 8 RAS\-only refresh or CAS\-before-RAS\ refresh cycles before proper device operation is achieved.
2. VIH(MIN) and VIL(MAX) are reference levels for measuring timing of input signals. Transition times are measured between VIH(MIN) and VIL(MAX) and are assumed to be 5ns for all inputs.
3. Measured with a load equivalent to 1 TTL loads and 100pF.
4. Operation within the tRCD(MAX) limit insures that tRAC(MAX) and be met. tRCD(MAX) is specified as a reference point only. If tRCD is greater than the specified tRCD(MAX) limit, then access time is
controlled exclusively by tCAC
.
5. Assumes that tRCD > tRCD(MAX).
6. tOFF(MIN) and tOEZ(MAX) define the time at which the output achieves the open circuit condition and are not referenced VOH or VOL
.
7. tWCS, tRWD, tCWD and tAWD are non restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS > tWCS(MIN), the cycle is an early write cycle and the data
output will remain high impedance for the duration of the cycle. If tCWD > tCWD(MIN), tRWD > tRWD(MIN) and tAWD > tAWD(MIN), then the cycle is a read-modify-write cycle and the data output will
contain the data read from the selected address. If neither of the above conditions is satisfied, the condition of the data out is indeterminate.
8. Either tRCH or tRRH must be satisfied for a read cycle.
9. These parameters are referenced to CAS\ falling edge in early write cycles and to W\ falling edge in read-modify-write cycles.
10. Operation within the tRAD(MAX) limit insures that tRAC(MAX) can be met. tRAD(MAX) is specified as a reference point only. If tRAD is greater than the specified tRAS(MAX) limit, then access time is
controlled by tAA
.
11. These specifications are applied in the test mode.
12. In test mode read cycle, the value of tRAC, tAA, tCAC is delayed by 2ns to 5ns for the specified values. These parameters should be specified in test mode cycles by adding the above value to the specified
value in this data sheet.
13. If tRASS > 100 us, then RAS\ precharge time must use tRPS instead of tRP
.
14. For RAS\-only refresh and burst CAS\-before-RAS\ refresh mode, 2048 cycles of burst refresh must be executed within 32ms before and after self refresh, in order to meet refresh specification.
15. For distributed CAS\-before-RAS\ with 15.6us interval CAS\-before-RAS\ refresh should be executed with in 15.6us immediately before and after self refresh in order to meet refresh specification.
AS4LC4M4
AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice.
Rev. 0.3 7/06
6