i PEM
2.4Gb
2.4Gb SDRAM-DDR
Austin Semiconductor, Inc.
AS4DDR32M72PBG1
PIN DEFINITIONS / FUNCTIONAL DESCRIPTION
BGA Location
B5,B6,N10,V6,V7
C4,C5,M10,U9,U10
C2,C3,M9,U7,U8
B3,B4,N11,V8,V9
B7,C8,N2,U2,V3
B8,B9,N4,V4,V5
C9,C10,N1U3,U4
C6,C7M4,U5,U6
D1,D2,M8,T8,T9
D10,D11M3,T1,T2
D3,D4M7,T10,T11
J4,L4,L2,K3,K9,L10,
L8,J8,L9,J9,K2,K10,
J2
L3, J3
H1,H3,J10,M11
D5,D6,D7,D8,D9,E1,E2,
E3,E4,E5,E6,E7,E8,E9,
E10,E11,F1,F2,F3,F4,
F5,F6,F7,F8,F9,F10,
G1,G2,G3,G4,G5,G7,
G8,G9,G10,G11,H2,H3,
H5,H7,H8,H9,H10,H11,
M1,M2,M5,N4,N5,N7,N8,
N9,P1,P2,P3,P4,P5,P6,
P7,P8,P9,P10,P11,R1,
R2,R3,R4,R5,R6,R7,R8,
R9,R10,R11,T3,T4,T5,
T6,T7,
T6 T7
K6
A2,A10,H6,J5,J11,L1,
L7,M6,W2,W10
A4,A5,A7,A8,B1,B2,J1,
J7,K4,K8,L5,L11,V1,
V11,W4,W5,W7,W8
A3,A6,A9,A11,B2,B10,
C1,C11,G6,J6,K1,K5,
K7,K11,L6,N6,U1,U11,
V2,V10,W1,W3,W6,W9,
W11
Symbol
CKEx
CKx
CKx\
CSx\
CASx\
RASx\
WEx\
DQMLx
DQMHx
DQSLx
DQSHx
Ax
BAx
DNU
Type
Description
Clock Enable, enabler of all on silicon clock circuitry
Clock input (active HIGH) part of a differential pair (1 pair per x16 bits)
Clock input (active LOW) part of a differential pair (1pair per x16 bits)
Chip Selects, one per x16 bits (active LOW)
Column Address Select (1 per x16 bits)
Row Address Select (1 per x16 bits)
WRITE enable input (active LOW, 1 per x16 bits)
CNTL Input
Array Address input providing ROW addresses for ACTIVE commands and
ADDR Input the COLUMN address and AUTO PRECHARGE bit (A10) for READ/WRITE
commands
Input
Bank Address select input
Future Use
DQx
Input/Output Data, bi-directional Input/Output pins
Vref
VCC
VCCQ
Supply
Supply
Supply
SSTL-25 Voltage Reference
Core Power Supply
IO Power Supply
VSS
Supply
Ground Return
UNPOPULATED
Unpopulated ball matrix location (location registration aid)
AS4DDR32M72PBG1
Rev. 0.1 06/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
3
AUSTIN [ AUSTIN SEMICONDUCTOR ]
