i PEM
2.4Gb
2.4Gb SDRAM-DDR
Austin Semiconductor, Inc.
AS4DDR32M72PBG1
FIGURE 2 - CAS LATENCY
T0
T1
T2
T2n
T3
T3n
FIGURE 3 - EXTENDED MODE REGISTER
DEFINITION
BA
1
BA
0
A
12
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
Address Bus
CLK
CLK
COMMAND
READ
NOP
CL = 2
NOP
NOP
01
11
Operating Mode
QFC#
DS
DLL
Extended Mode
Register (Ex)
DQS
DQ
E0
0
DLL
Enable
Disable
T0
CLK
CLK
T1
T2
T2n
T3
T3n
E1
1
Drive Strength
Normal
Reduced
QFC# Function
Disabled
Reserved
COMMAND
READ
NOP
CL = 2.5
NOP
NOP
0
1
E22
0
-
DQS
DQ
E12
E11
E10 E9
E8
0
-
E7
0
-
E6
0
-
E5
0
-
E4
0
-
E3
0
-
E2, E1, E0
Valid
-
Operating Mode
Reserved
Reserved
Burst Length = 4 in the cases shown
Shown with nominal tAC and nominal tDSDQ
DATA
TRANSITIONING DATA
DON'T CARE
0
-
0
-
0
-
0
-
1. E14 and E13 must be "0, 1" to select the Extended Mode Register (vs. the base Mode Register)
2. The QFE# function is not supported.
OUTPUT DRIVE STRENGTH
The normal full drive strength for all outputs are specified to
be SSTL2, Class II. The DDR SDRAM supports an option for
reduced drive. This option is intended for the support of the
lighter load and/or point-to-point environments. The selection
of the reduced drive strength will alter the DQs and DQSs
from SSTL2, Class II drive strength to a reduced drive strength,
which is approximately 54 percent of the SSTL2, Class II
drive strength.
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to perform a
NOP to the selected DDR SDRAM (CS# is LOW). This
prevents unwanted commands from being registered during
idle or wait states. Operations already in progress are not
affected.
LOAD MODE REGISTER
The Mode Registers are loaded via inputs A0-12. The LOAD
MODE REGISTER command can only be issued when all
banks are idle, and a subsequent executable command
cannot be issued until t
MRD
is met.
DLL ENABLE/DISABLE
The DLL must be enabled for normal operation. DLL enable
is required during power-up initialization and upon returning
to normal operation after having disabled the DLL for the
purpose of debug or evaluation. (When the device exits self
refresh mode, the DLL is enabled automatically.) Any time
the DLL is enabled, 200 clock cycles must occur before a
READ command can be issued.
ACTIVE
The ACTIVE command is used to open (or activate) a row in
a particular bank for a subsequent access. The value on
the BA0, BA1 inputs selects the bank, and the address
provided on inputs A0-12 selects the row. This row remains
active (or open) for accesses until a PRECHARGE
command is issued to that bank. A PRECHARGE command
must be issued before opening a different row in the same
bank.
COMMANDS
The Truth Table provides a quick reference of available
commands. This is followed by a written description of each
command.
DESELECT
The DESELECT function (CS# HiGH) prevents new
commands from being executed by the DDR SDRAM. The
SDRAM is effectively deselected. Operations already in
progress are not affected.
AS4DDR32M72PBG1
Rev. 0.1 06/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
7
AUSTIN [ AUSTIN SEMICONDUCTOR ]
