iPEM
2.4Gb SDRAM-DDR
AS4DDR32M72PBG1
Austin Semiconductor, Inc.
15. The CLK/CLK# inpꢁt reference level (fꢀr timing referenced tꢀ CLK/CLK#)
is the pꢀint at ohich CLK and CLK# crꢀss; the inpꢁt reference level fꢀr
signals ꢀther than CLK/CLK# is VREF.
NOTES:
1. All vꢀltages referenced tꢀ VSS.
2. Tests fꢀr AC timing, ICC, and electrical AC and DC characteristics may be
cꢀndꢁcted at nꢀminal reference/sꢁpply vꢀltage levels, bꢁt the related
specificatiꢀns and device ꢀperatiꢀn are gꢁaranteed fꢀr the fꢁll vꢀltage
range specified.
16. Inpꢁts are nꢀt recꢀgnized as valid ꢁntil VREF stabilizes. Exceptiꢀn: dꢁring the
periꢀd befꢀre VREF stablizes, CKE < 0.3 x VCCQ is recꢀgnized as LOW.
17. The ꢀꢁtpꢁt timing reference level, as measꢁred at the timing reference
pꢀint indicated in Nꢀte 3, is VTT.
18. tHZ and tLZ transitiꢀns ꢀccꢁr in the same access time oindꢀos as valid
data transitiꢀns. These parameters are nꢀt referenced tꢀ a specific vꢀltage
level, bꢁt specify ohen the device ꢀꢁtpꢁt is nꢀ lꢀnger driving (HZ) ꢀr
begins driving (LZ).
3. Oꢁtpꢁts measꢁred oith eqꢁivalent lꢀad:
V
TT
50Ω
19. The maximꢁm limit fꢀr this parameter is nꢀt a device limit. The device oill
ꢀperate oith a greater valꢁe fꢀr this parameter, bꢁt system perfꢀrmance
(bꢁs tꢁrnarꢀꢁnd) oill degrade accꢀrdingly.
Reference
Output
(VOUT
Point
30pF
)
20. This is nꢀt a device limit. The device oill ꢀperate oith a negative valꢁe, bꢁt
system perfꢀrmance cꢀꢁld be degraded dꢁe tꢀ bꢁs tꢁrnarꢀꢁnd.
21. It is recꢀmmended that DQS be valid (HIGH ꢀr LOW) ꢀn ꢀr befꢀre the
WRITE cꢀmmand. The case shꢀon (DQS gꢀing frꢀm High-Z tꢀ lꢀgic LOW)
applies ohen nꢀ WRITEs oere previꢀꢁsly in prꢀgress ꢀn the bꢁs. If a
previꢀꢁs WRITE oas in prꢀgress, DQS cꢀꢁld be HIGH dꢁring this time,
depending ꢀn tDQSS.
22. MIN (tRC ꢀr tRFC) fꢀr ICC measꢁrements is the smallest mꢁltiple ꢀf tCK that
meets the minimꢁm absꢀlꢁte valꢁe fꢀr the respective parameter. tRAS
(MAX) fꢀr ICC measꢁrements is the largest mꢁltiple ꢀf tCK that meets the
maximꢁm absꢀlꢁte valꢁe fꢀr tRAS.
4. AC timing and ICC tests may ꢁse a VIL-tꢀ-VIH soing ꢀf ꢁp tꢀ 1.5V in the test
envirꢀnment, bꢁt inpꢁt timing is still referenced tꢀ VREF (ꢀr tꢀ the crꢀssing
pꢀint fꢀr CLK/CLK#), and parameter specificatiꢀns are gꢁaranteed fꢀr the
specified AC inpꢁt levels ꢁnder nꢀrmal ꢁse cꢀnditiꢀns. The minimꢁm sleo
rate fꢀr the inpꢁt signals ꢁsed tꢀ test the device is 1V/ns in the range
betoeen VIL(AC) and VIH(AC).
5. The AC and DC inpꢁt level specificatiꢀns are as defined in the SSTL_2
Standard (i.e., the receiver oill effectively soitch as a resꢁlt ꢀf the signal
crꢀssing the AC inpꢁt level, and oill remain in that state as lꢀng as the
signal dꢀes nꢀt ring back abꢀve [belꢀo] the DC inpꢁt LOW [HIGH] level).
6. VREF is expected tꢀ eqꢁal VCCQ/2 ꢀf the transmitting device and tꢀ track
variatiꢀns in the DC level ꢀf the same. Peak-tꢀ-peak nꢀise (nꢀncꢀmmꢀn
mꢀde) ꢀn VREF may nꢀt exceed 2 percent ꢀf the DC valꢁe. Thꢁs, frꢀm
VCCQ/2, VREF is allꢀoed 25mV fꢀr DC errꢀr and an additiꢀnal 25mV fꢀr
AC nꢀise. This measꢁrement is tꢀ be taken at the nearest VREF by-pass
capacitꢀr.
7. VTT is nꢀt applied directly tꢀ the device. VTT is a system sꢁpply fꢀr signal
terminatiꢀn resistꢀrs, is expected tꢀ be set eqꢁal tꢀ VREF and mꢁst track
variatiꢀns in the DC level ꢀf VREF.
8. VID is the magnitꢁde ꢀf the difference betoeen the inpꢁt level ꢀn CLK and
the inpꢁt level ꢀn CLK#.
23. The refresh periꢀd 64ms. This eqꢁates tꢀ an average refresh rate ꢀf
Hꢀoever, an AUTO REFRESH cꢀmmand mꢁst be asserted at least ꢀnce
every 70.3µs; bꢁrst refreshing ꢀr pꢀsting by the DRAM cꢀntrꢀller greater
than eight refresh cycles is nꢀt allꢀoed.
24. The I/O capacitance per DQS and DQ byte/grꢀꢁp oill nꢀt differ by mꢀre
than this maximꢁm amꢀꢁnt fꢀr any given device.
25. The valid data oindꢀo is derived by achieving ꢀther specificatiꢀns - tHP
(tCK/2), tDQSQ, and tQH (tQH = tHP - tQHS). The data valid oindꢀo derates
directly pꢀrpꢀrtiꢀnal oith the clꢀck dꢁty cycle and a practical data valid
oindꢀo can be derived. The clꢀck is allꢀoed a maximꢁm dꢁty cycle
variatiꢀn ꢀf 45/55. Fꢁnctiꢀnality is ꢁncertain ohen ꢀperating beyꢀnd a
45/55 ratiꢀ. The data valid oindꢀo derating cꢁrves are prꢀvided
26. Referenced tꢀ each ꢀꢁtpꢁt grꢀꢁp: LDQS oith DQ0-DQ7; and UDQS oith
DQ8-DQ15 ꢀf each chip.
27. This limit is actꢁally a nꢀminal valꢁe and dꢀes nꢀt resꢁlt in a fail valꢁe.
CKE is HIGH belꢀo fꢀr dꢁty cycles ranging betoeen 50/50 and 45/55.
dꢁring REFRESH cꢀmmand periꢀd (tRFC [MIN]) else CKE is LOW (i.e.,
dꢁring standby)
9. The valꢁe ꢀf VIX and VMP are expected tꢀ eqꢁal VCCQ/2 ꢀf the transmitting
device and mꢁst track variatiꢀns in the DC level ꢀf the same.
10. ICC is dependent ꢀn ꢀꢁtpꢁt lꢀading and cycle rates. Specified valꢁes are
ꢀbtained oith minimꢁm cycle time oith the ꢀꢁtpꢁts ꢀpen.
11. Enables ꢀn-chip refresh and address cꢀꢁnters.
28. Tꢀ maintain a valid level, the transitiꢀning edge ꢀf the inpꢁt mꢁst:
a) Sꢁstain a cꢀnstant sleo rate frꢀm the cꢁrrent AC level thrꢀꢁgh tꢀ the
target AC level, VIL(AC) ꢀr VIH(AC).
12. ICC specificatiꢀns are tested after the device is prꢀperly initialized, and is
averaged at the defined cycle rate.
13. This parameter is nꢀt tested bꢁt gꢁaranteed by design. tA = 25OC, f = 1
MHz
b) Reach at least the target AC level.
c) After the AC target level is reached, cꢀntinꢁe tꢀ maintain at least the
target DC level, VIL(DC) ꢀr VIH(DC).
14. Cꢀmmand/Address inpꢁt sleo rate = 0.5V/ns. Fꢀr 266 MHz oith sleo rates
1V/ns and faster, tIS and tIH are redꢁced tꢀ 900ps. If the sleo rate is less
than 0.5V/ns, timing mꢁst be derated: tIS has an additiꢀnal 50ps per each
100mV/ns redꢁctiꢀn in sleo rate frꢀm the 500mV/ns. tIH has 0ps added,
that is, it remains cꢀnstant. If the level, sleo rate exceeds 4.5V/ns,
fꢁnctiꢀnality is ꢁncertain.
FIGURE A - PULL-DOWN CHARACTERISTICS
FIGURE B - PULL-UP CHARACTERISTICS
0
160
-20
Maximum
140
Minimum
-40
120
-60
-80
Nominal low
Nominal high
Nominal high
100
80
-100
-120
-140
-160
-180
-200
Nominal low
60
Minimum
40
20
0
Maximum
0.0
0.5
1.0
1.5
2.0
2.5
0.0
0.5
1.0
CCQ -
1.5
VOUT (V)
2.0
2.5
V
V
OUT (V)
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS4DDR32M72PBG1
Rev. 0.1 06/09
14
AUSTIN [ AUSTIN SEMICONDUCTOR ]
