i PEM
2.4Gb
2.4Gb SDRAM-DDR
Austin Semiconductor, Inc.
AS4DDR32M72PBG
OPERATING MODE
The normal operating mode is selected by issuing a MODE
REGISTER SET command with bits A7-A12 each set to zero,
and bits A0-A6 set to the desired values. A DLL reset is initiated
by issuing a MODE REGISTER SET command with bits A7 and
A9-A12 each set to zero, bit A8 set to one, and bits A0-A6 set to
the desired values. Although not required, JEDEC specifications
recommend when a LOAD MODE REGISTER command is
issued to reset the DLL, it should always be followed by a
LOAD MODE REGISTER command to select normal operating
mode.
All other combinations of values for A7-A12 are reserved for
future use and/or test modes. Test modes and reserved states
should not be used because unknown operation or
incompatibility with future versions may result.
FIGURE 1 - MODE BURST DEFINITION
BA
1
BA
0
A
12
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
Address Bus
Mode Register (Mx)
0*
0*
Operating Mode
CAS Latency
BT
Burst Length
* M14 and M13
(BA0 and BA1 must be
"0, 0" to select
the base mode register
(vs. the extended
mode register).
Burst Length
M2 M1 M0
0
0
0
0
1
1
1
1
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
M3 = 0
Reserved
2
4
8
Reserved
Reserved
Reserved
Reserved
M3 = 1
Reserved
2
4
8
Reserved
Reserved
Reserved
Reserved
EXTENDED MODE REGISTER
The extended mode register controls functions beyond those
controlled by the mode register; these additional functions are
DLL enable/disable, output drive strength, and QFC#. These
functions are controlled via the bits shown in Figure 3. The
extended mode register is programmed via the LOAD MODE
REGISTER command to the mode register (with BA0 = 1 and
BA1 = 0) and will retain the stored information until it is
programmed again or the device loses power. The enabling of
the DLL should always be followed by a LOAD MODE
REGISTER command to the mode register (BA0/BA1 both LOW)
to reset the DLL.
The extended mode register must be loaded when all banks
are idle and no bursts are in progress, and the controller must
wait the specified time before initiating any subsequent
operation. Violating either of these requirements could result
in unspecified operation.
M12
0
0
-
M11
0
0
-
M10
0
0
-
M9
0
0
-
M8
0
1
-
M7
0
0
-
M3
0
1
Burst Type
Sequential
Interleaved
M6 M5 M4
0
0
0
0
1
1
1
1
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
CAS Latency
Reserved
Reserved
2
Reserved
Reserved
Reserved
2.5
Reserved
M6-M0
Valid
Valid
-
Operating Mode
Normal Operation
Normal Operation/Reset DLL
All other states reserved
AS4DDR32M72PBG
Rev. 1.2 06/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
7
AUSTIN [ AUSTIN SEMICONDUCTOR ]
