i PEM
4.8 Gb SDRAM-DDR2
Gb
Austin Semiconductor, Inc.
AS4DDR264M72PBG
64Mx72 DDR2 SDRAM
iNTEGRATED Plastic Encapsulated Microcircuit
FEATURES
DDR2 Data rate = 667, 533, 400
Available in Industrial, Enhanced and Extended Temp
Package:
•
255 Plastic Ball Grid Array (PBGA), 25 x 32mm
•
1.27mm pitch
Differential data strobe (DQS, DQS#) per byte
Internal, pipelined, double data rate architecture
4n-bit prefetch architecture
DLL for alignment of DQ and DQS transitions with
clock signal
Eightinternal banks for concurrent operation
(Per DDR2 SDRAM Die)
Programmable Burst lengths: 4 or 8
Auto Refresh and Self Refresh Modes (I/T Version)
On Die Termination (ODT)
Adjustable data – output drive strength
1.8V
±0.1V
power supply and I/O (VCC/VCCQ)
Programmable CAS latency: 3, 4, 5, 6 or 7
Posted CAS additive latency: 0, 1, 2, 3, 4 or 5
Write latency = Read latency - 1* tCK
Organized as 64M x 72 w/ support for x80
Weight: AS4DDR264M72PBG ~ 3.5 grams typical
NOTE: Self Refresh Mode available on Industrial and Enhanced temp. only
BENEFITS
SPACE conscious PBGA defined for easy
SMT manufacturability (50 mil ball pitch)
Reduced part count
47% I/O reduction vs Individual CSP approach
Reduced trace lengths for lower parasitic
capacitance
Suitable for hi-reliability applications
Upgradable to 128M x 72 density in future
FUNCTIONAL BLOCK DIAGRAM
2
Ax, BA0-1
ODT
VRef
VCC
VCCQ
VSS
VSSQ
VCCL
VSSDL
CS0\
CS1\
CS2\
CS3\
CS4\
UDMx, LDMx
UDSQx,UDSQx\
LDSQx, LDSQx\
RASx\,CASx\,WEx\
CKx,CKx\,CKEx
A
2
2
2
3
3
A
VCCL
VSSDL
2
2
2
3
3
B
VCCL
VSSDL
2
2
2
3
3
C
VCCL
VSSDL
2
2
2
3
3
2
2
2
3
3
D
VCCL
VSSDL
DQ64-79
DQ0-15 B
DQ16-31 C
DQ32-47 D
DQ48-63
AS4DDR264M72PBG
Rev. 1.5 11/07
Austin Semiconductor, Inc.
●
Austin, Texas
●
512.339.1188
●
www.austinsemiconductor.com
1
AUSTIN [ AUSTIN SEMICONDUCTOR ]
