i PEM
4.8 Gb SDRAM-DDR2
Gb
Austin Semiconductor, Inc.
AS4DDR264M72PBG1
FIGURE 4 - POWER-UP AND INITIALIZATION
Notes appear on page 7
V
DD
V
DD
L
V
DD
Q
V
TT
1
V
REF
T0
t
CK
Ta0
Tb0
Tc0
Td0
Te0
Tf0
Tg0
Th0
Ti0
Tj0
Tk0
Tl0
Tm0
t
VTD1
CK#
CK
t
CL
t
CL
LVCMOS 2
SSTL_18
2
CKE
LOW LEVEL LOW LEVEL
ODT
Comman d
3
NOP4
PRE
LM 5
LM
6
LM 7
LM 8
9
PRE
10
REF
REF
LM 11
LM 12
LM 13
Vali
d
16
DM
15
3
Address
A10 = 1
Code
Code
Code
Code
A10 = 1
Code
Code
Code
Vali
d
15
DQS
DQ
15
High-Z
High-Z
High-Z
R
TT
T = 200µs (MIN)
Power-up:
V
DD
and stable
clo ck
(CK,
CK#)
T = 400ns
(MIN) 16
t RPA
EMR(2)
t MRD
t MRD
EMR(3)
EMR
t MRD
t MRD
t RPA
t RF
C
t RF
C
See note 17
t MRD
t MRD
EMR with
OCD exit
t MRD
MR without
DLL RE
SET
MR with
DLL RE
SET
EMR with
OCD
default
200
cycles
of
CK
are re
quire d before
a READ
comman d can be
issued.
Normal
operation
Indicates a
break
in
time s
cale
Don
’t care
AS4DDR264M72PBG1
Rev. 3.0 6/09
Austin Semiconductor, Inc.
●
Austin, Texas
●
512.339.1188
●
www.austinsemiconductor.com
5
AUSTIN [ AUSTIN SEMICONDUCTOR ]
