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AS4DDR264M65PBG1R-38/IT 参数 Datasheet PDF下载

AS4DDR264M65PBG1R-38/IT图片预览
型号: AS4DDR264M65PBG1R-38/IT
PDF下载: 下载PDF文件 查看货源
内容描述: 64Mx64 DDR2 SDRAM瓦特/双控总线集成塑封微电路 [64Mx64 DDR2 SDRAM w/ DUAL CONTROL BUS iNTEGRATED Plastic Encapsulated Microcircuit]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 28 页 / 242 K
品牌: AUSTIN [ AUSTIN SEMICONDUCTOR ]
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iPEM  
4.2 Gb SDRAM-DDR2  
Austin Semiconductor, Inc.  
AS4DDR264M65PBG1  
FIGURE 9 - EXTENDED MODE REGISTER 3 (EMR3) DEFINITION  
1
BA22  
1
BA1 BA0 An A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0  
Address bus  
Extended mode  
register (Ex)  
16 15 14  
MRS  
n
12 11 10  
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
E15 E14  
Mode Register Set  
Mode register (MR)  
0
0
1
1
0
1
0
1
Extended mode register (EMR)  
Extended mode register (EMR2)  
Extended mode register (EMR3)  
Notes:  
1.Mode bits (En) with corresponding address balls (An) greater than A12 are reserved for future use and must be programmed to “0.”  
2.E16 (BA2) must be programmed to “0” on this device and is reserved for future use.  
EXTENDED MODE REGISTER 2  
The extended mode register 2 (EMR2) controls functions  
beyond those controlled by the mode register. Currently all  
bits in EMR2 are reserved, as shown in Figure 8. The EMR2  
is programmed via the LM command and will retain the stored  
information until it is programmed again or the device loses  
power. Reprogramming the EMR will not alter the contents  
of the memory array, provided it is performed correctly.  
EMR3 must be loaded when all banks are idle and no bursts  
are in progress, and the controller must wait the specifi ed  
time tMRD before initiating any subsequent operation.  
Violating either of these requirements could result in  
unspecified operation.  
COMMAND TRUTH TABLES  
The following tables provide a quick reference of DDR2  
SDRAM available commands, including CKE power-down  
modes, and bank-to-bank commands.  
EMR2 must be loaded when all banks are idle and no bursts  
are in progress, and the controller must wait the specified  
time tMRD before initiating any subsequent operation.  
Violating either of these requirements could result in  
unspecified operation.  
EXTENDED MODE REGISTER 3  
The extended mode register 3 (EMR3) controls functions  
beyond those controlled by the mode register. Currently, all  
bits in EMR3 are reserved, as shown in Figure 9. The EMR3  
is programmed via the LM command and will retain the stored  
information until it is programmed again or the device loses  
power. Reprogramming the EMR will not alter the contents  
of the memory array, provided it is performed correctly.  
Austin Semiconductor, Inc.  
Austin, Texas 512.339.1188 www.austinsemiconductor.com  
AS4DDR264M65PBG1  
Rev. 0.5 06/08  
13