i PEM
4.2 Gb SDRAM-DDR2
Gb
Austin Semiconductor, Inc.
AS4DDR264M64PBG1
CAS LATENCY (CL)
The CAS latency (CL) is defined by bits M4-M6, as shown
in Figure 5. CL is the delay, in clock cycles, between the
registration of a READ command and the availability of the
first bit of output data. The CL can be set to 3, 4, 5, 6 or 7
clocks, depending on the speed grade option being used.
DDR2 SDRAM does not support any half-clock latencies.
Reserved states should not be used as unknown operation
or incompatibility with future versions may result.
DDR2 SDRAM also supports a feature called posted CAS
additive latency (AL). This feature allows the READ command
to be issued prior to
t
RCD (MIN) by delaying the
internal command to the DDR2 SDRAM by AL clocks.
Examples of CL = 3 and CL = 4 are shown in Figure 6; both
assume AL = 0. If a READ command is registered at clock
edge
n,
and the CL is
m
clocks, the data will be available
nominally coincident with clock edge
n+m (this assumes
AL = 0).
FIGURE 6 - CAS LATENCY (CL)
T0
CK#
CK
Command
READ
T1
T2
T3
T4
T5
T6
NOP
NOP
NOP
NOP
NOP
NOP
DQS, DQS#
DQ
CL = 3 (AL = 0)
DO
n
DO
n+1
DO
n+2
DO
n+3
T0
CK#
CK
Command
READ
T1
T2
T3
T4
T5
T6
NOP
NOP
NOP
NOP
NOP
NOP
DQS, DQS#
DQ
CL = 4 (AL = 0)
DO
n
DO
n+1
DO
n+2
DO
n+3
Transitioning data
Don’t care
Notes:
1. BL = 4.
2. Posted CAS# additive latency (AL) = 0.
3. Shown with nominal
t
AC,
t
DQSCK, and
t
DQSQ.
AS4DDR264M64PBG1
Rev. 0.5 06/08
Austin Semiconductor, Inc.
●
Austin, Texas
●
512.339.1188
●
www.austinsemiconductor.com
9
AUSTIN [ AUSTIN SEMICONDUCTOR ]
