i PEM
4.2 Gb SDRAM-DDR2
Gb
Austin Semiconductor, Inc.
AS4DDR264M64PBG1
64Mx64 DDR2 SDRAM w/ SHARED CONTROL BUS
iNTEGRATED Plastic Encapsulated Microcircuit
FEATURES
DDR2 Data rate = 667, 533, 400
Available in Industrial, Enhanced and Extended Temp
Package:
•
Proprietary Enchanced Die Stacked iPEM
•
208 Plastic Ball Grid Array (PBGA), 16 x 23mm
•
1.00mm ball pitch
Differential data strobe (DQS, DQS#) per byte
Internal, pipelined, double data rate architecture
4n-bit prefetch architecture
DLL for alignment of DQ and DQS transitions with
clock signal
Eightinternal banks for concurrent operation
(Per DDR2 SDRAM Die)
Programmable Burst lengths: 4 or 8
Auto Refresh and Self Refresh Modes (I/T Version)
On Die Termination (ODT)
Adjustable data – output drive strength
1.8V
±0.1V
common core power and I/O supply
Programmable CAS latency: 3, 4, 5, 6 or 7
Posted CAS additive latency: 0, 1, 2, 3, 4 or 5
Write latency = Read latency - 1* tCK
Organized as 64M x 64
Weight: AS4DDR264M64PBG1 ~ 2.0 grams typical
NOTE: Self Refresh Mode available on Industrial and Enhanced temp. only
BENEFITS
58% Space Savings
49% I/O reduction vs Individual CSP approach
Reduced part count
Reduced trace lengths for lower parasitic
capacitance
Suitable for hi-reliability applications
Upgradable to 128M x 64 density in future
FUNCTIONAL BLOCK DIAGRAM
Ax, BA0-2
ODT
VRef
VCC
VCCQ
VSS
VSSQ
VSSQ
VCCL
VSSDL
VCCQ
VSSQ
VCCL
A
VSSDL
B
VCCQ
VSSQ
VCCL
VSSDL
C
VCCQ
VSSQ
VCCL
VSSDL
D
CS\
WE\
RAS\
CAS\
CKE\
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
ODT
UDMx, LDMx
UDSQx,UDSQx\
LDSQx, LDSQx\
CKx,CKx\
A
DQ0-15 B
DQ16-31 C
DQ32-47 D
DQ48-63
AS4DDR264M64PBG1
Rev. 0.5 06/08
Austin Semiconductor, Inc.
●
Austin, Texas
●
512.339.1188
●
www.austinsemiconductor.com
1
AUSTIN [ AUSTIN SEMICONDUCTOR ]
