i PEM
2.4 Gb SDRAM-DDR2
Gb
Austin Semiconductor, Inc.
AS4DDR232M72PBG
BGA Locations
L6
F4, F16, G5, G15, K12
L13, L2, K1, M8, N6
G4, G16, K13, M6, K2
G1, G13, K16, K4, M12
F12, G2, K15, L5, M11
F1, G12, M9, L16, L4,
F2, F13, L15, M4, M10
E4, F15, M13, M7, M2
E2, E13, M15, M5, N11
E5, E7, E11, N12, N5
F6, F8, F10, K6, L11
E6, E10, F5, K5, L12
F7, F11, G6, L7, L10
CKEx
CSx\
RASx\
CASx\
Wex\
UDMx
LDMx
UDQSx
UDQSx\
LDQSx
LDQSx\
CNTL Input
CNTL Input
CNTL Input
CNTL Input
CNTL Input
CNTL Input
CNTL Input
CNTL Input
CNTL Input
CNTL Input
CNTL Input
Clock enable which activates all on silicon clocking circuitry
Chip Selects, one for each 16 bits of the data bus width
Command input which along with CAS\, WE\ and CS\ define operations
Command input which along with RAS\, WE\ and CS\ define operations
Command input which along with RAS\, CAS\ and CS\ define operations
One Data Mask cntl. for each upper 8 bits of a x16 word
One Data Mask cntl. For each lower 8 bits of a x16 word
Data Strobe input for upper byte of each x16 word
Differential input of UDQSx, only used when Differential DQS mode is enabled
Data Strobe input for lower byte of each x16 word
Differential input of LDQSx, only used when Differential DQS mode is enabled
Array Address inputs providing ROW addresses for Active commands, and
the column address and auto precharge bit (A10) for READ/WRITE commands
Symbol
ODT
CKx, CKx\
Type
CNTL Input
CNTL Input
Description
On-Die-Termination: Registered High enables on data bus termination
Differential input clocks, one set for each x16bits
A7, A8, A9, A10, B7,
Ax
Input
B8, B9, B10, C7, C8,
C9, C10, D7
D8, D9, D10
DNU
Future Input
E8, E9
BA0, BA1
Input
A2, A3, A4, A13, A14,
DQx
Input/Output
A15, B1, B2, B3, B4,
B13, B14, B15, B16,
C1, C2, C3, C4, C13,
C14, C15, C16, D1, D2,
D3, D4, D13, D14, D15,
D16, E1, E16, M1, M16,
N1, N2, N3, N4, N7, N8,
N9, N10, N13, N14,
N15, N16, PP1, P2, P3,
P4, P7, P8, P9, P10,
P13, P14, P15, P16,
R1, R2, R3, R4, R7, R8,
R9, R10, R13, R14,
R15, R16, T2, T3, T4,
T7, T8, T9, T10, T13,
T14, T15
E12
Vref
Supply
B11, B12, C5, C6,E3,
VCC
Supply
F3, G3, H3, H12, H16,
J3, J12, J16, K3, L3,
M3, P11, P12, R5, R6,
T16
A11, A12, D5, D6, H4,
VCCQ
Supply
H15, J4, J15, T5, T6
A5, A6, A16, B5, B6,
VSS
Supply
C11, C12, D11, D12,
E14, F14, G14, H1, H2,
H14, J1, J2, J5, J13,
J14, K14, L14, M14, P5,
P6, R11, R12, T1, T11,
T12, H5, H13
G7, G8, G9, G10, H7,
VSSQ
Supply
H8, H9, H10, J7, J8, J9,
J10, K7, K8, K9, K10
E15, F9, G11, H6, H11,
NC
J6, J11, K11, L1, L8, L9,
A1
UNPOPULATED
AS4DDR232M72PBG
Rev. 2.0 5/07
Bank Address inputs
Data bidirectional input/Output pins
SSTL_18 Voltage Reference
Core Power Supply
I/O Power
Core Ground return
I/O Ground return
No connection
Unpopulated ball matrix location (location registration aid)
Austin Semiconductor, Inc.
●
Austin, Texas
●
512.339.1188
●
www.austinsemiconductor.com
3
AUSTIN [ AUSTIN SEMICONDUCTOR ]
