iPEM
2.4 Gb SDRAM-DDR2
Austin Semiconductor, Inc.
AS4DDR232M72PBG
following two sets of conditions (A or B) must be met to
obtain a stable supply state (stable supply defi ned as
2. For a minimum of 200 µs after stable power nd clock
(CK, CK#), apply NOP or DESELECT commands and
take CKE HIGH.
3. Wait a minimum of 400ns, then issue a PRECHARGE
ALL command.
4. Issue an LOAD MODE command to the EMR(2). (To
issue an EMR(2) command, provide LOW to BA0,
provide HIGH to BA1.)
5. Issue a LOAD MODE command to the EMR(3). (To
issue an EMR(3) command, provide HIGH to BA0 and
BA1.)
6. Issue an LOAD MODE command to the EMR to enable
DLL. To issue a DLLENABLE command, provide LOW
to BA1 andA0, provide HIGH to BA0. Bits E7, E8, and
E9 can be set to “0” or “1”; Micron recommends setting
them to “0”.
7. Issue a LOAD MODE command for DLL RESET. 200
cycles of clock input is required to lock the DLL. (To
issue a DLL RESET, provide HIGH to A8 and provide
LOW to BA1, and BA0.) CKE must be HIGH the entire
time.
V
, VCCQ, VREF, and VTT are between their
mCinCimum and maximum values as stated in Table20);
A. (single power source) The VCC voltage ramp from
300mV to VCC (MIN) must take no longer than
200ms; during the VCC voltage ramp, |VCC - VCCQ|
± 0.3V. Once supply voltage ramping is complete
(when VCCQ crosses VCC (MIN)), Table 20
specifications apply.
• VCC, V are driven from a single power converter
outputCCQ
• VTT is limited to 0.95V MAX
• VREF tracks VCCQ/2; VREF must be within
± 0.3V with respect to VCCQ/2 during supply ramp
time
• VCCQ > VREF at all times
B. (multiple power sources) V > VCCQ must be
maintained during supply voltaCgCe ramping, for both
AC and DC levels, until supply voltage ramping
completes (VCCQ crosses VCC [MIN]). Once supply
voltage ramping is complete, Table 20 specifications
apply.
8. Issue PRECHARGEALL command.
9. Issue two or more REFRESH commands, followed
by a dummy WRITE.
• Apply VCC before or at the same time as
VCCQ; VCC voltage ramp time must be < 200ms
from when VCC ramps from 300mV to VCC (MIN)
• Apply VCCQ before or at the same time as VTT; the
VCCQ voltage ramp time from when VCC (MIN) is
achieved to when VCCQ (MIN) is achieved must be
<500ms; while VCC is ramping, current can be
supplied from VCC through the device to VCCQ
• VREF must track VCCQ/2, VREF must be within
± 0.3V with respect to VCCQ/2 during supply ramp
time; VCCQ > VREF must be met at all times
• Apply VTT; The VTT voltage ramp time from when
VCCQ (MIN) is achieved to when VTT (MIN) is achieved
must be no greater than 500ms
Austin Semiconductor, Inc.
● Austin, Texas ● 512.339.1188 ● www.austinsemiconductor.com
AS4DDR232M72PBG
Rev. 2.0 5/07
5
AUSTIN [ AUSTIN SEMICONDUCTOR ]
