i PEM
2.1 Gb SDRAM-DDR2
Gb
Austin Semiconductor, Inc.
AS4DDR232M64PBG
following two sets of conditions (A or B) must be met to
obtain a stable supply state (stable supply defi ned as
V
CC
, V
CCQ
, V
REF
, and V
TT
are between their
minimum and maximum values as stated in Table20);
A. (single power source) The V
CC
voltage ramp from
300mV to V
CC
(MIN) must take no longer than
200ms; during the V
CC
voltage ramp, |VCC - VCCQ|
± 0.3V. Once supply voltage ramping is complete
(when V
CCQ
crosses V
CC
(MIN)), Table 20
specifications apply.
• V
CC
, V
CCQ
are driven from a single power converter
output
• V
TT
is limited to 0.95V MAX
• V
REF
tracks V
CCQ/2
; V
REF
must be within
± 0.3V with respect to V
CCQ/2
during supply ramp
time
• V
CCQ
> V
REF
at all times
B. (multiple power sources) V
CC
> V
CCQ
must be
maintained during supply voltage ramping, for both
AC and DC levels, until supply voltage ramping
completes (V
CCQ
crosses V
CC
[MIN]). Once supply
voltage ramping is complete, Table 20 specifications
apply.
• Apply V
CC
before or at the same time as
V
CCQ
; V
CC
voltage ramp time must be < 200ms
from when V
CC
ramps from 300mV to V
CC
(MIN)
• Apply V
CCQ
before or at the same time as V
TT
; the
V
CCQ
voltage ramp time from when V
CC
(MIN) is
achieved to when V
CCQ
(MIN) is achieved must be
<500ms; while V
CC
is ramping, current can be
supplied from V
CC
through the device to V
CCQ
• VREF must track VCCQ/2, VREF must be within
± 0.3V with respect to V
CCQ/2
during supply ramp
time; V
CCQ
> V
REF
must be met at all times
• Apply V
TT
; The V
TT
voltage ramp time from when
V
CCQ
(MIN) is achieved to when V
TT
(MIN) is achieved
must be no greater than 500ms
2. For a minimum of 200
µ
s after stable power nd clock
(CK, CK#), apply NOP or DESELECT commands and
take CKE HIGH.
3. Wait a minimum of 400ns, then issue a PRECHARGE
ALL command.
4. Issue an LOAD MODE command to the EMR(2). (To
issue an EMR(2) command, provide LOW to BA0,
provide HIGH to BA1.)
5. Issue a LOAD MODE command to the EMR(3). (To
issue an EMR(3) command, provide HIGH to BA0 and
BA1.)
6. Issue an LOAD MODE command to the EMR to enable
DLL. To issue a DLL ENABLE command, provide LOW
to BA1 and A0, provide HIGH to BA0. Bits E7, E8, and
E9 can be set to “0” or “1”; Micron recommends setting
them to “0”.
7. Issue a LOAD MODE command for DLL RESET. 200
cycles of clock input is required to lock the DLL. (To
issue a DLL RESET, provide HIGH to A8 and provide
LOW to BA1, and BA0.) CKE must be HIGH the entire
time.
8. Issue PRECHARGE ALL command.
9. Issue two or more REFRESH commands, followed
by a dummy WRITE.
AS4DDR232M64PBG
Rev. 1.3 6/09
Austin Semiconductor, Inc.
●
Austin, Texas
●
512.339.1188
●
www.austinsemiconductor.com
5
AUSTIN [ AUSTIN SEMICONDUCTOR ]
