iPEM
2.1 Gb SDRAM-DDR2
Austin Semiconductor, Inc.
AS4DDR232M64PBG
DDRII ICC SPECIFICATIONS AND CONDITIONS
Units
Parameter
Symbol
-3
-38
-5
Operating Current: One bank active-precharge
tCL=tCK(ICC), tRC=tRC(ICC), tRAS=tRAS MIN(ICC);
CKE is HIGH, CS\ is HIGH between valid commands;
Address bus switching, Data bus switching
ICC0
480
440
400
mA
Operating Current: One bank active-READ-
precharge current
IOUT=0ma; BL=4, CL=CL(ICC), AL=0; tCK =
tCK(ICC), tRC-tRC(ICC), tRAS=tRAS MIN(ICC),
tRCD=tRCD(ICC); CKE is HIGH, CS\ is HIGH
between valid commands; Address bus is switching;
Precharge POWER-DOWN current
ICC1
ICC2P
ICC2Q
650
520
480
mA
mA
mA
All banks idle; tCK-tCK(ICC); CKE is LOW; Other
control and address bus inputs are stable; Data bus
inputs are floating
25
25
25
Precharge quiet STANDBY current
All banks idle; tCK=tCK(ICC); CKE is HIGH, CS\ is
HIGH; Other control and address bus inputs are
stable; Data bus inputs are floating
225
250
180
200
145
170
Precharge STANDBY current
All banks idle; tCK-=tCK(ICC); CKE is HIGH, CS\ is
HIGH; Other control and address bus inputs are
switching; Data bus inputs are switching
ICC2N
ICC3P
mA
mA
Active POWER-DOWN current
MRS[12]=0
145
32
125
32
105
32
All banks open; tCK=tCK(ICC); CKE is
LOW; Other control and address inputs
MRS[12]=1
are stable; Data bus inputs are floating
Active STANDBY current
All banks open; tCK=tCK(ICC), tRAS MAX(ICC),
tRP=tRP(ICC); CKE is HIGH, CS\ is HIGH between
valid commands; Other control and address bus
inputs are switching; Data bus inputs are switching
ICC3N
ICC4W
275
700
225
575
200
500
mA
mA
Operating Burst WRITE current
All banks open, continuous burst writes; BL=4,
CL=CL(ICC), tRP=tRP(ICC); CKE is HIGH, CS\ is
HIGH between valid commands; Address bus inputs
Operating Burst READ current
All banks open, continuous burst READS, Iout=0mA;
BL=4, CL=CL(ICC), AL=0; tCL=tCK(ICC), tRAS=tRAS
MAX(ICC), tRP=tRP(ICC); CKE is HIGH, CS\ is HIGH
between valid commands; Address and Data bus
inputs switching
ICC4R
750
625
550
mA
Burst REFRESH current
tCK=tCK(ICC); refresh command at every tRFC9ICC)
interval; CKE is HIGH, CS\ is HIGH between valid
commands; Other control, Address and Data bus
inputs are switching
ICC5
ICC6
ICC7
600
25
550
25
500
25
mA
mA
mA
Self REFRESH current
CK and CK\ at 0V; CKE </= 0.2V; Other Control,
address and data inputs are floating.
Operating bank Interleave READ current:
All bank interleaving READS, IOUT = 0mA; BL=4,
CL=CL(ICC), AL=tRCD(ICC)-1xtCK(ICC);
tCK=tCK(ICC), tRC=tRC(ICC), tRRD=tRRD(ICC);
CKE is HIGH, CS\ is HIGH between valid commands;
Address bus inputs are stable during deselects; Data
1025
1025
1025
Austin Semiconductor, Inc.
●
Austin, Texas
●
512.339.1188
●
www.austinsemiconductor.com
AS4DDR232M64PBG
Rev. 1.3 6/09
23
AUSTIN [ AUSTIN SEMICONDUCTOR ]
