i PEM
1.2 Gb SDRAM-DDR
Gb
Austin Semiconductor, Inc.
AS4DDR16M72PBG
PIN DEFINITIONS / FUNCTIONAL DESCRIPTION
BGA Locations
SYMBOL
F4, F16, G5, G15, K1, K12,
CKx, CKx\
L2, L13, N6, M8
DESCRIPTION
Clock: CKx and CKx\ are differential clock inputs. All address and control input signals
are sampled on the crossing of the positive edge of CKx and negative edge of CKx\.
Output data (DQ's and DQS) is referenced to the crossings of the differential clock
inputs.
Clock Enable: CKE controls the clock inputs. CKE high enables, CKE Low disables
the clock input pins. Driving CKE Low provides PRECHARGE POWER-DOWN. CKE
is synchronous for POWER-DOWN entry and exit, and for SELF REFRESH entry CKE
is Asynchronous for SELF REFRESH exit and for disabling the outputs. CKE must be
maintained HIGH throughout read and write accesses. Input buffers are disabled
during POWER-DOWN Input buffers are disabled during SELF REFRESH. CKE is an
SSTL-2 input but will detect an LVCMOS LOW level after VCC is applied
Chip Select: CSx\ enables the COMMAND register(s) of each of the five (5) contained
words. All commands are masked with CSx\ is registered HIGH. CSx\ provides for
external bank selection on systems with multiple banks. CSx\ is considered part of the
COMMAND CODE.
Command Inputs: RASx, CASx and Wex\ define the command being entered.
G4, G16, K2, K13, M6
CKEx
G1, G13, K4, K16, M12
CSx\
F4, F16, G5, G15, K1, K12, RASx\, CASx\,
L2, L13, N7, M9
Wex\
G4, G16, K2, K14, M7
Input Data Mask: DM is an input mask signal for write data. Input data is masked when
DQMLx, DQMHx
DQMLx or Hx is sampled HIGH at time of a WRITE access. DM is sampled on both
edges of DQSLx and DQSHx.
BA0, BA1
Bank Address Inputs: BA0, BA1, define which bank an ACTIVE READ, WRITE or
PRECHARGE Command is being applied.
Address Input: Provide the row address for Active commands, and the column address
and auto precharge bit (A10) for READ / WRITE commands to select one location out
of the memory array in the respective bank. A10 sampled during a PRECHARGE
command determines whether the PRECHARGE applies to one bank or all banks.
The address inputs also provide the op-code during a MODE RESISTER SET
command.
E8, E9
A7, A8, A9, A10, B7, B8,
B9, B10, C7, C8. C9, C10, A0-11, A12
D7
A2, A3, A4, A13, A14, B1,
B2, B3, B4, B13, B14, B15,
B16, C1, C2, C3, C4, C13,
C14, C15, C16, D1, D2, D3,
D4, D13, D14, D15, D16,
E1, E16, M1, M16, N1, N2, DQ0-79
N3, N4, N13, N14, N15,
N16, T2, T3, T4, T13, T14,
T15, N7, N8, N9, N10, P7,
P8, P9, P10, R7, R8, R9,
R10, T7, T8, T9, T10
E6, E7, E10, E11, F5, K5,
DQSLX, DQSHX
L12, N5, N12, E5
B11, B12, C5, C6, E3, F3,
G3, H3, H12, H16, J3, J12,
VCC
J16, K3, L3, M3, P11, P12,
R5, R6, T16
A11, A12, D5, D6, H4, H15,
VCCQ
J4, J15, T5, T6
A5, A6, A16, B5, B6, C11,
C12, D11, D12, E14, F14,
G14, H1, H2, H5, H13,
VSS
H14, J1, J2, J5, J13, J14,
K14, L14, P5, P6, R11.
R12, T1, T11, T12, M14
E12
AS4DDR16M72PBG
Rev. 2.1 06/09
Data I/O
Data Stobe: Output with read data, input with write data. DQS is edge-aligned with
read data, centered in write data. It is used to capture data
Core Power Supply
I/O Power Supply
Ground (Digital)
VREF
SSTL-2 Reference Voltage
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
4
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