AUSTIN SEMICONDUCTOR, INC.
SOLID
STATE DISK
STA
AS3SSD4GB8PBG
AS3SSD8GB8PBG
AS3SSD16GB5PBG
PRELIMINARY
Austin Semiconductor, Inc.
KEY FEATURES
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NAND FLASH Controller
(2) stacks, each containing (2 or 4) NAND components
Each NAND component, either a 4,8 or 16Gb device, based on the use of single
silicon and stacked silicon solutions
Providing a total bit density of either 4,8 or 16GB
Controller contained in base interposer
Fast ATA host to buffer transfer rates supporting True IDE, PIO/4 mode support
512Byte Sector Buffers
Flash Memory power-down logic
ECC correction = 6 Bytes within a 512 Byte sector
Automatic Sleep Mode
Burst Transfer rate, 16.67MB per second
Sustained Transfer rate: 6.7MB per second
Sophisticated Wear Leveling
ARCHITECTURE
The PATA controller in the PATA Solid State Drive utilizes a 32-bit RISC architecture which provides for
direct connection of one, two or four NAND flash memory devices (2 per channel). An on-chip error
correction code (ECC) and cyclic redundancy check (CRC) unit generates the required code bytes
facilitating error detection and correction of up to six bytes per 512 byte data sector. On the fly code
byte generation for read and write operations minimizes ECC performance impacts.
The controller’s flash memory interface allows the direct connection of up to 10 chips and support
Samsung (NAND) type flash memory. ASI PATA Solid State Drives use single level cell (SLC) Samsung
NAND Flash Memory devices.
AS3SSD4GB8PBG, AS3SSD8GB8PBG, AS3SSD16GB5PBG
Rev. 1.3 07/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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AUSTIN [ AUSTIN SEMICONDUCTOR ]
