COTS PEM
COTS
BOOT SECTOR
BOOT SECTOR FLASH
Austin Semiconductor, Inc.
AS29LV016
STANDBY MODE
When the system is not reading or writing to the device,
it can place the device in the standby mode. In this mode,
current consumption is greatly reduced, and the outputs
are placed in the high impedance state, independent of
the OE# input.
The device enters the CMOS standby mode when the
CE# and RESET# pins are both held at V
CC
± 0.3 V.
(Note that this is a more restricted voltage range than
V
IH
.) If CE# and RESET# are held at V
IH
, but not within
V
CC
± 0.3 V, the device will be in the standby mode, but
the standby current will be greater. The device requires
standard access time (t
CE
) for read access when the device
is in either of these standby modes, before it is ready to
read data.
If the device is deselected during erasure or programming,
the device draws active current until the operation is
completed.
I
CC3
and I
CC4
represents the standby current specification
shown in the table in DC Characteristics on page 27.
RESET#: HARDWARE RESET PIN
The RESET# pin provides a hardware method of resetting
the device to reading array data. When the system drives
the RESET# pin to V
IL
for at least a period of t
RP
, the
device
immediately terminates
any operation in
progress, tristates all data output pins, and ignores all
read/write attempts for the duration of the RESET# pulse.
The device also resets the internal state machine to
reading array data. The operation that was interrupted
should be reinitiated once the device is ready to accept
another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET# pulse.
When RESET# is held at V
SS
±0.3 V, the device draws
CMOS standby current (I
CC4
). If RESET# is held at V
IL
but
not within V
SS
±0.3 V, the standby current will be greater.
The RESET# pin may be tied to the system reset circuitry.
A system reset would thus also reset the Flash memory,
enabling the system to read the boot-up firmware from
the Flash memory.
If RESET# is asserted during a program or erase
operation, the RY/BY# pin remains a
0
(busy) until the
internal reset operation is complete, which requires a time
of t
READY
(during Embedded Algorithms). The system can
thus monitor RY/BY# to determine whether the reset
operation is complete. If RESET# is asserted when a
program or erase operation is not executing (RY/BY# pin
is
1),
the reset operation is completed within a time of
t
READY
(not during Embedded Algorithms). The system can
read data t
RH
after the RESET# pin returns to V
IH
.Refer to
the tables in AC Characteristics on page 29 for RESET#
parameters and to Figure 13, on page 30 for the timing
diagram.
AUTOMATIC SLEEP MODE
The automatic sleep mode minimizes Flash device energy
consumption. The device automatically enables this mode
when addresses remain stable for t
ACC
+ 30 ns. The
automatic sleep mode is independent of the CE#, WE#,
and OE# control signals. Standard address access timings
provide new data when addresses are changed. While in
sleep mode, output data is latched and always available
to the system. I
CC4
in the DC Characteristics on page 27
represents the automatic sleep mode current specification.
AS29LV016
Rev. 2.1 10/08
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
8
AUSTIN [ AUSTIN SEMICONDUCTOR ]
