FLASH
Austin Semiconductor, Inc.
erase circuits are disabled, and the device resets. Subsequent
writes are ignored until V
CC
is greater than V
LKO
. The system
must provide the proper signals to the control pins to prevent
unintentional writes when V
CC
is greater than V
LKO
.
Write Pulse “Glitch” Protection
Noise pulses of less than 5ns (typical) on OE\, CE\, or WE\
do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE\ = V
IL
,
CE\ = V
IH
or WE\ = V
IH
. To initiate a write cycle, CE\ and WE\
must be a logical zero while OE\ is a logical one.
Power-Up Write Inhibit
If WE\ = CE\ = V
IL
and OE\ = V
IH
during power up, the
device does not accept commands on the rising edge of WE\.
The internal state machine is automatically reset to reading
array data on power-up.
AS29F010
Reading Array Data
The device is automatically set to reading array data after
device power-up. No commands are required to retrieve data.
The device is also ready to read array data after completing an
Embedded Program or Embedded Erase algorithm.
The system
must
issue the reset command to re-enable the
device for reading array data if DQ5 goes high, or while in the
autoselect mode. See the “Reset Command” section, next.
See also “Requirements for Reading Array Data” in the
“Device Bus Operations” section for more information. The
Read Operations table provides the read parameters, and the
Read Operation Timings diagram shows the timing diagram.
Reset Command
Writing the reset command to the device resets the device
to reading array data. Address bits are don’t care for this
command.
The reset command may be written between the sequence
cycles in an erase command sequence before erasing begins.
This resets the device to reading array data. Once erasure
begins, however, the device ignores reset commands until the
operation is complete.
The reset command may be written between the sequence
cycles in a program command sequence before programming
begins. This resets the device to reading array data. Once
programming begins, however, the device ignores reset com-
mands until the operation is complete.
The reset command may be written between the sequence
cycles in an autoselect command sequence. Once in the
autoselect mode, the reset command
must
be written to return
to reading array data.
If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to reading array
data.
COMMAND DEFINITIONS
Writing specific address and data commands or sequences
into the command register initiates device operations. The
Command Definitions table defines the valid register command
sequences. Writing
incorrect address and data values
or
writing them in the
improper sequence
resets the device to
reading array data.
All addresses are latched on the falling edge of WE\ or
CE\, whichever happens first. Refer to the appropriate timing
diagrams in the “AC Characteristics” section.
TABLE 3: Autoselect Codes (High Voltage Method)
DESCRIPTION
Manufacturer ID
Device ID
Sector Protection
Verification
CE\
L
L
OE\
L
L
A16 to A13 to
WE\
A9
A14 A10
H
H
X
X
X
X
V
ID
V
ID
A8
to
A7
X
X
A6
L
L
A5
to
A2
X
X
A1
L
L
A0
L
H
DQ7 to DQ0
01h
20h
01h
(protected)
L
L
H
SA
X
V
ID
X
L
X
H
L
00h
(unprotected)
NOTE:
L = Logic Low = V
IL
, H = Logic High = V
IH
, SA = Sector Address, X = Don’t Care
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS29F010
Rev. 2.3 12/08
6
AUSTIN [ AUSTIN SEMICONDUCTOR ]
