FLASH
Austin Semiconductor, Inc.
Autoselect Command Sequence
The autoselect command sequence allows the host
system to access the manufacturer and devices codes, and
determine whether or not a sector is protected. The Command
Definitions table shows the address and data requirements.
This method is an alternative to that shown in the Autoselect
Codes (High Voltage Method) table, which is intended for
PROM programmers and requires V
ID
on address bit A9.
The auto select command sequence is initiated by writing
two unlock cycles, followed by the autoselect command. The
device then enters the autoselect mode, and the system may
read at any address any number of times, without initiating
another command sequence.
A read cycle at address XX00h or retrieves the
manufacturer code. A read cycle at address XX01h returns the
device code. A read cycle containing a sector address (SA)
and the address 02h in returns 01h if that sector is protected, or
00h if it is unprotected. Refer to the Sector Address tables for
valid sector addresses.
The system must write the reset command to exit the
autoselect mode and return to reading array data.
AS29F010
command sequence is initiated by writing two unlock cycles,
followed by a set-up command. Two additional unlock write
cycles are then followed by the chip erase command, which in
turn invokes the Embedded Erase algorithm. The device does
not
require the system to preprogram prior to erase. The
Embedded Erase algorithm automatically preprograms and
verifies the entire memory for an all zero data pattern prior to
electrical erase. The system is not required to provide any
controls or timings during these operations. The Command
Definitions table shows the address and data requirements for
the chip erase command sequence.
Any commands written to the chip during the Embedded
Erase algorithm are ignored.
The system can determine the status of the erase
operation by using DQ7 or DQ6. See “Write Operation Status”
for information on these status bits. When the Embedded Erase
algorithm is complete, the device returns to reading array data
and addresses are no longer latched.
Figure 2 illustrates the algorithm for the erase operation.
See the Erase/Program Operations tables in “AC
Characteristics” for parameters, and the Chip /Sector Erase
Operation Timings for timing waveforms.
Byte Program Command Sequence
Programming is a four-bus-cycle operation. The program
command sequence is initiated by writing two unlock write
cycles, followed by the program set-up command. The
program address and data are written next, which in turn initiate
the Embedded Program algorithm. The system is
not
required
to provide further controls or timings. The device
automatically provides internally generated program pulses and
verify the programmed cell margin. The Command Definitions
take shows the address and data requirements for the byte
program command sequence.
When the Embedded Program algorithm is complete, the
device then returns to reading array data and addresses are no
longer latched. The system can determine the status of the
program operation by using DQ7 or DQ6. See “Write Operation
Status” for information on these status bits.
Any commands written to the device during the
Embedded Program Algorithm are ignored.
Programming is allowed in any sequence and across
sector boundaries.
A bit cannot be programmed from a “0”
back to a “1”.
Attempting to do so may halt the operation and
set DQ5 to “1”, or cause the Data\ Polling algorithm to indicate
the operation was successful. However, a succeeding read will
show that the data is still “0”. Only erase operations can
convert a “0” to a “1”.
FIGURE 1: PROGRAM OPERATION
Chip Erase Command Sequence
Chip erase is a six-bus-cycle operation. The chip erase
AS29F010
Rev. 2.3 12/08
NOTE:
7
See the appropriate Command Definitions table for program
command sequence.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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