FLASH
AS29F010
Austin Semiconductor, Inc.
Bia I mrꢄ be ꢂerd ra rnꢄ rddꢂeꢃꢃ, rnd iꢃ vrlid rfaeꢂ ahe ꢂiꢃing
edge pf ahe finrl WE\ ꢁslꢃe in ahe cpmmrnd ꢃeqsence (ꢁꢂipꢂ ap
ahe ꢁꢂpgꢂrm pꢂ eꢂrꢃe pꢁeꢂraipn), rnd dsꢂing ahe ꢃecapꢂ eꢂrꢃe
aime-psa.
Dsꢂing rn Embedded Pꢂpgꢂrm pꢂ Eꢂrꢃe rlgpꢂiahm
pꢁeꢂraipn, ꢃscceꢃꢃive ꢂerd cꢄcleꢃ ap rnꢄ rddꢂeꢃꢃ crsꢃe DQ6 ap
apggle. (The ꢃꢄꢃaem mrꢄ sꢃe eiaheꢂ OE\ pꢂ CE\ ap cpnaꢂpl ahe
ꢂerd cꢄcleꢃ.) When ahe pꢁeꢂraipn iꢃ cpmꢁleae, DQ6 ꢃapꢁꢃ
apggling.
WRITE OPERATION STATUS
The device ꢁꢂpvideꢃ ꢃeveꢂrl biaꢃ ap deaeꢂmine ahe ꢃarasꢃ pf
r oꢂiae pꢁeꢂraipn: DQ3, DQ5, DQ6, rnd DQ7. Trble 5 rnd ahe
fpllpoing ꢃsbꢃecaipnꢃ deꢃcꢂibe ahe fsncaipnꢃ pf aheꢃe biaꢃ. DQ7
rnd DQ6 erch pffeꢂ r meahpd fpꢂ deaeꢂmining oheaheꢂ r
ꢁꢂpgꢂrm pꢂ eꢂrꢃe pꢁeꢂraipn iꢃ cpmꢁleae pꢂ in ꢁꢂpgꢂeꢃꢃ. Theꢃe
ahꢂee biaꢃ rꢂe diꢃcsꢃꢃed fiꢂꢃa.
DQ7: Data\ Polling
Afaeꢂ rn eꢂrꢃe cpmmrnd ꢃeqsence iꢃ oꢂiaaen, if rll ꢃecapꢂꢃ
The Drar\ Pplling bia, DQ7, indicraeꢃ ap ahe hpꢃa ꢃꢄꢃaem
oheaheꢂ rn Embedded Algpꢂiahm iꢃ in ꢁꢂpgꢂeꢃꢃ pꢂ cpmꢁleaed.
Drar\ Pplling iꢃ vrlid rfaeꢂ ahe ꢂiꢃing edge pf ahe finrl WE\ ꢁslꢃe
in ahe ꢁꢂpgꢂrm pꢂ eꢂrꢃe cpmmrnd ꢃeqsence.
FIGURE 3: DATA\ POLLING ALGORITHM
Dsꢂing ahe Embedded Pꢂpgꢂrm rlgpꢂiahm, ahe device
psaꢁsaꢃ pn DQ7 ahe cpmꢁlemena pf ahe drasm ꢁꢂpgꢂrmmed ap
DQ7. When ahe Embedded Pꢂpgꢂrm rlgpꢂiahm iꢃ cpmꢁleae, ahe
device psaꢁsaꢃ ahe drasm ꢁꢂpgꢂrmmed ap DQ7. The ꢃꢄꢃaem
msꢃa ꢁꢂpvide ahe ꢁꢂpgꢂrm rddꢂeꢃꢃ ap ꢂerd vrlid ꢃarasꢃ
infpꢂmraipn pn DQ7. If r ꢁꢂpgꢂrm rddꢂeꢃꢃ frllꢃ oiahin r
ꢁꢂpaecaed ꢃecapꢂ, Drar\ Pplling pn DQ7 iꢃ rcaive fpꢂ
rꢁꢁꢂpximraelꢄ 2µꢃ, ahen ahe device ꢂeasꢂnꢃ ap ꢂerding rꢂꢂrꢄ
drar.
Dsꢂing ahe Embedded Eꢂrꢃe rlgpꢂiahm, Drar\ Pplling
ꢁꢂpdsceꢃ r “0” pn DQ7. When ahe Embedded Eꢂrꢃe rlgpꢂiahm
iꢃ cpmꢁleae, Drar\ Pplling ꢁꢂpdsceꢃ r “±” pn DQ7. Thiꢃ iꢃ
rnrlpgpsꢃ ap ahe cpmꢁlemena/aꢂse drasm psaꢁsa deꢃcꢂibed fpꢂ
ahe Embedded Pꢂpgꢂrm rlgpꢂiahm: ahe eꢂrꢃe fsncaipn chrngeꢃ
rll ahe biaꢃ in r ꢃecapꢂ ap “±”; ꢁꢂipꢂ ap ahiꢃ, ahe device psaꢁsaꢃ
ahe “cpmꢁlemena,” pꢂ “0”. The ꢃꢄꢃaem msꢃa ꢁꢂpvide rn
rddꢂeꢃꢃ oiahin rnꢄ pf ahe ꢃecapꢂꢃ ꢃelecaed fpꢂ eꢂrꢃsꢂe ap ꢂerd
vrlid ꢃarasꢃ infpꢂmraipn pn DQ7.
Afaeꢂ rn eꢂrꢃe cpmmrnd ꢃeqsence iꢃ oꢂiaaen, if rll ꢃecapꢂꢃ
ꢃelecaed fpꢂ eꢂrꢃing rꢂe ꢁꢂpaecaed, Drar\ Pplling pn DQ7 iꢃ
rcaive fpꢂ rꢁꢁꢂpximraelꢄ ±00µꢃ, ahen ahe device ꢂeasꢂnꢃ ap
ꢂerding rꢂꢂrꢄ drar. If npa rll ꢃelecaed ꢃecapꢂꢃ rꢂe ꢁꢂpaecaed, ahe
Embedded Eꢂrꢃe rlgpꢂiahm eꢂrꢃeꢃ ahe snꢁꢂpaecaed ꢃecapꢂꢃ, rnd
ignpꢂeꢃ ahe ꢃelecaed ꢃecapꢂꢃ ahra rꢂe ꢁꢂpaecaed.
When ahe ꢃꢄꢃaem deaecaꢃ DQ7 hrꢃ chrnged fꢂpm ahe
cpmꢁlemena ap aꢂse drar, ia crn ꢂerd vrlid drar ra DQ7-DQ0 pn
ahe following ꢂerd cꢄcleꢃ. Thiꢃ iꢃ becrsꢃe DQ7 mrꢄ chrnge
rꢃꢄnchꢂpnpsꢃlꢄ oiah DQ0-DQ6 ohile Osaꢁsa Enrble (OE\) iꢃ
rꢃꢃeꢂaed lpo. The Drar\ Pplling Timingꢃ (Dsꢂing Embedded
Algpꢂiahmꢃ) figsꢂe in ahe “AC Chrꢂrcaeꢂiꢃaicꢃ” ꢃecaipn
illsꢃaꢂraeꢃ ahiꢃ.
Trble 5 ꢃhpoꢃ ahe psaꢁsaꢃ fpꢂ Drar\ Pplling pn DQ7.
Figsꢂe 3 ꢃhpoꢃ ahe Drar\ Pplling rlgpꢂiahm.
NOTE:
±) VA = Vrlid rddꢂeꢃꢃ fpꢂ ꢁꢂpgꢂrmming. Dsꢂing r ꢃecapꢂ eꢂrꢃe pꢁeꢂraipn,
r vrlid rddꢂeꢃꢃ iꢃ rn rddꢂeꢃꢃ oiahin rnꢄ ꢃecapꢂ ꢃelecaed fpꢂ eꢂrꢃsꢂe. Dsꢂing
chiꢁ eꢂrꢃe, r vrlid rddꢂeꢃꢃ iꢃ rnꢄ npn-ꢁꢂpaecaed ꢃecapꢂ rddꢂeꢃꢃ.
2) DQ7 ꢃhpsld be ꢂechecked even if DQ5 = “±” becrsꢃe DQ7 mrꢄ chrnge
ꢃimslarnepsꢃlꢄ oiah DQ5.
DQ6: Toggle Bit I
Tpggle bia I pn DQ6 indicraeꢃ oheaheꢂ rn Embedded
Pꢂpgꢂrm pꢂ Eꢂrꢃe rlgpꢂiahm iꢃ in ꢁꢂpgꢂeꢃꢃ pꢂ cpmꢁleae. Tpggle
AS29F010
AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice.
Rev. 2.3 12/08
10
AUSTIN [ AUSTIN SEMICONDUCTOR ]
