PEM
Austin Semiconductor, Inc.
AS28F128J3M
Q-Flash
Plastic Encapsulated Microcircuit
128Mb, x8 and x16 Q-FLASH Memory
Even Sectored, Single Bit per Cell Architecture
Features
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100% Pin and Function compatible to Intel’s MLC Family
NOR Cell Architecture
2.7V to 3.6V VCC
2.7V to 3.6V or 5V VPEN (Programming Voltage)
Asynchronous Page Mode Reads
Manufacturer’s ID Code:
!
MT28F128J3MRG
Micron
0x2Ch
Industry Standard Pin-Out
Fully compatible TTL Input and Outputs
Common Flash Interface [CFI]
Scalable Command Set
Automatic WRITE and ERASE Algorithms
5.6us per Byte effective programming time
128 bit protection register
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64-bit unique device identifier
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64-bit user programmable OTP cells
Enhanced data protection feature with use of VPEN=VSS
Security OTP block feature
100,000 ERASE cycles per BLOCK
Automatic Suspend Options:
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Block ERASE SUSPEND-to-READ
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Block ERASE SUSPEND-to-PROGRAM
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PROGRAM SUSPEND-to-READ
Available Operating Ranges:
[-ET] -40
o
C to +105
o
C
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Enhanced
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Mil-Temperature [-XT] -55
o
C to +125
o
C
A
A1
PIN ASSIGNMENT
1
2
3
4
5
6
7
8
A6
A8
VPEN
A13
VCC
A18
A22
B
A2
VSS
A9
CE0
A14
A25
A19
CE1
C
A3
A7
A10
A12
A15
DNU
A20
A21
D
A4
A5
A11
RP\
DNU
DNU
A16
A17
E
DQ8
DQ1
DQ9
DQ3
DQ4
DNU
DQ15
STS
F
BYTE\
DQ0
DQ10
DQ11 DQ12
DNU
DNU
OE\
G
A23
A0
DQ2
VCCQ
DQ5
DQ6
DQ14
WE\
H
CE2
DNU
VCC
VSS
DQ13
VSS
DQ7
A24
64-Ball FBGA
A22
CE1
A21
A20
A19
A18
A17
A16
VCC
A15
A14
A13
A12
CE0
VPEN
RP\
A11
A10
A9
A8
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
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NC
WE\
OE\
STS
DQ15
DQ7
DQ14
DQ6
VSS
DQ13
DQ5
DQ12
DQ4
VCCQ
VSS
DQ11
DQ3
DQ10
DQ2
VCC
DQ9
DQ1
DQ8
DQ0
A0
BYTE\
A23
CE2
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For in-depth functional product detail and Timing Diagrams,
please reference Micron’s full product Datasheet:
MT28F640J3
Rev. L Dated 04/16/04
A7
A6
A5
A4
A3
A2
A1
General Description
ASI’s, AS28F128J3M Enhanced or Mil-Temp variant of Micron’s
Q-Flash family of devices, is a nonvolatile, electrically block-
erasable (FLASH), programmable memory device manufactured
using Micron’s 0.15um process technology.
This device
containing 134,217,728 bits organized as either 16,777,218 (x8)
or 8,388,608 bytes (x16). The device is uniformly sectored with
one hundred and twenty eight 128KB ERASE blocks.
This device features in-system block locking. They also have a
Common FLASH Interface [CFI] that permits software algorithms
to be used for entire families of devices. The software is device-
independent, JEDEC ID-independent with forward and backward
compatibility.
AS28F128J3MRG
Revision 5.0 11/23/04
Austin Semiconductor, Inc. reserves the right to change products or modify product specifications with appropriate notification
For Additional Products and Information visit out Web site at
www.austinsemiconductor.com
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AUSTIN [ AUSTIN SEMICONDUCTOR ]
