UVEPROM
Austin Semiconductor, Inc.
READ/OUTPUT DISABLE
When the outputs of two or more AS27C256 are connected in
parallel on the same bus, the output of any particular device in
the circuit can be read with no interference from the compet-
ing outputs of the other devices. To read the output of the
selected AS27C256, a low-level signal is applied to E\ and G\.
All other devices in the circuit should have their outputs
disabled by applying a high-level signal to one of these pins.
Output data is accessed at pins DQ0 through DQ7.
AS27C256
FLASHRITE PULSE PROGRAMMING
The AS27C256 EPROM is programmed by using the AMD
FLASHRITE Pulse programming algorithm as illustrated by the
flowchart in Figure 1. This algorithm programs the device in a
nominal time of 4 seconds. Actual programming time varies as
a function of the programmer used.
Data is presented in parallel (eight bits) on pins DQ0 to DQ7.
Once addresses and data are stable, E\ is pulsed.
The FLASHRITE Pulse programming algorithm uses initial
pulses of 100 microseconds (µs) followed by a byte-verifica-
tion step to determine when the addressed byte has been suc-
cessfully programmed. Up to 25 100µs pulses per byte are
provided before a failure is recognized.
The programming mode is achieved when V
PP
= 12.75V,
V
CC
= 6.25V, G\ = V
IH
, and E\ = V
IL
. More than one device can be
programmed when the devices are connected in parallel. Loca-
tions can be programmed in any order. When the AMD
FLASHRITE Pulse programming routine is completed, all bits
are verified with V
CC
= V
PP
= 5V.
LATCHUP IMMUNITY
Latchup immunity on the AS27C256 is a minimum of 250mA on
all inputs and outputs. This feature provides latchup
im-
munity beyond any potential transients at the printed
cir-
cuit board level when the EPROM is interfaced to industry
standard TTL or MOS logic devices. Input/output layout
approach controls latchup without compromising performance
or packing density.
POWER DOWN
Active I
CC
supply current can be reduced from 25mA (AS27C256-
12 through AS27C256-25) to 1mA (TTL-level inputs) or 300µA
(CMOS-level inputs) by applying a high TTL/CMOS signal to
the E\ pin. In this mode all outputs are in the high-impedance
state.
PROGRAM INHIBIT
Programming can be inhibited by maintaining a high-level
input on E\.
ERASURE
Before programming, the AS27C256 is erased by exposing the
chip through the transparent lid to a high-intensity ultraviolet
light (wavelength 2537 Å). EPROM erasure before program-
ming is necessary to ensure that all bits are in the logic-high
state. Logic-lows are programmed into the desired locations. A
programmed logic-low can be erased only by ultraviolet light.
The recommended minimum exposure dose (UV intensity x ex-
posure time) is 15W•s/cm
2
. A typical 12mW/cm
2
, filterless UV
lamp erases the device in 21 minutes. The lamp should be
located about 2.5cm above the chip during erasure. After era-
sure, all bits are in the high state. It should be noted that normal
ambient light contains the correct wavelength for erasure; there-
fore, when using the AS27C256, the window should be covered
with an opaque label.
PROGRAM VERIFY
Programmed bits can be verified with V
PP
= 12.75V when G\ =
V
IL
, and E\ = V
IH
.
SIGNATURE MODE
The signature mode provides access to a binary code
iden-
tifying the manufacturer and device type. This mode is acti-
vated when A9 is forced to 12V ±0.5V. Two identifier bytes are
accessed by A0 (terminal 10); i.e., A0=V
IL
accesses the manu-
facturer code, which is output on DQ0-DQ7; A0=V
IH
accesses
the device code, which is also output on DQ0-DQ7. All other
addresses must be held at VIL. Each byte contains odd parity
on bit DQ7. The manufacturer code for these devices is 01h
and the device code is 10h.
AS27C256
Rev. 2.0 7/06
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
4
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