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AS1419AECA-MIL 参数 Datasheet PDF下载

AS1419AECA-MIL图片预览
型号: AS1419AECA-MIL
PDF下载: 下载PDF文件 查看货源
内容描述: 14位, 800ksps的采样A / D转换器,带有关断 [14 Bit, 800ksps Sampling A/D Converter with Shutdown]
分类和应用: 转换器
文件页数/大小: 20 页 / 998 K
品牌: AUSTIN [ AUSTIN SEMICONDUCTOR ]
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ADC  
AS1419  
AS1419A  
Austin Semiconductor, Inc.  
Full-Scale and Offset Adjustment  
Differential Inputs  
Figure 11a shows the ideal input/output characteristics  
for the AS1419. The code transitions occur midway between  
successive integer LSB values (i.e., –FS + 0.5LSB, – FS + 1.5LSB,  
–FS + 2.5LSB,... FS – 1.5LSB, FS – 0.5LSB). The output is two’s  
complement binary with 1LSB = FS – (– FS)/16384 = 5V/16384 =  
305.2µV. In applications where absolute accuracy is important,  
offset and full-scale errors can be adjusted to zero. Offset error  
must be adjusted before full-scale error. Figure 11b shows the  
extra components required for full-scale error adjustment. Zero  
offset is achieved by adjusting the offset applied to the –AIN  
The AS1419 has a unique differential sample-and-hold  
circuit that allows rail-to-rail inputs. The ADC will always  
convert the difference of +AIN – (–AIN) independent of the  
common mode voltage (see Figure 11a). The common mode  
rejection holds up to extremely high frequencies, see Figure  
10a. The only requirement is that both inputs can not exceed  
theAVDD orAVSS power supply voltages. Integral nonlinearity  
errors (INL) and differential nonlinearity errors (DNL) are  
independent of the common mode voltage, however, the  
bipolar zero error (BZE) will vary. The change in BZE is  
typically less than 0.1% of the common mode voltage. Dynamic  
performance is also affected by the common mode voltage.  
THD will degrade as the inputs approach either power supply  
rail, from 86dB with a common mode of 0V to 76dB with a  
common mode of 2.5Vor – 2.5V. Differential inputs allow greater  
flexibility for accepting different input ranges. Figure 10b shows  
a circuit that converts a 0V to 5V analog input signal with only  
an additional buffer that is not in the signal path.  
input. For zero offset error, apply –152µV (i.e., – 0.5LSB) at +AIN  
and adjust the offset at the –AIN input until the output code  
flickers between 0000 0000 0000 00 and 1111 1111 1111 11. For  
full-scale adjustment, an input voltage of 2.499544V (FS/2 –  
1.5LSBs) is applied to +AIN and R2 is adjusted until the output  
code flickers between 0111 1111 1111 10 and 0111 1111 1111 11.  
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.  
AS1419 & AS1419A  
Rev. 1.5 08/09  
12