Oscillator SMD, spread spectrum, programmable
APSSO 7050
APSSO 5032
Output clock switching characteristics
Description
Test conditions
Min
45
Typ
Max Unit
Duty cycle
HCMOS @ Vdd/2
Output clock rise / fall
2.25V~3.6V Vdd
55
4.0
2.4
10
%
ns
ns
ms
0.2-0.8Vdd, 2.25-3.6 Vdd, Cl=30
0.2-0.8Vdd, 2.25-3.6Vdd, Cl=15
From power on
3
Start up time
Electrical characteristics
Discription
Test conditions
3.0 ~ 3.6 V Vdd
Min
Typ
Max Unit
Input characteristics (Pin 1) VIL, Low-level input voltage
TO Tri-state or power-down
0.2 Vdd
V
VIH, High-level input voltage
TO Enable output or no connect
3.0 ~ 3.6 V Vdd
VIN = 0V
0.7 Vdd
V
80
10
µA
µA
IIL, Input low current
VIN = Vdd
IIH, Input high current
Output characteristics VOL, Low-level output voltage
3.0 V ~ 3.6 V Vdd, 8 mA IOL
2.25 V ~ 3.6 V Vdd, -8 mA IOL
2.25 ~ 3.6 Vdd, OUTPUT FREQ £ 200 MHz
2.25 ~ 3.6V Vdd, VIN = 0.7V
3.6V Vdd
0.4
V
V
Vdd - 0.4
50
VOHCMOS, High-level CMOS voltage
Power supply current (unloaded)
Input pull-up resistor
35
90
mA
ð þ
µA
70
20
Tri-state leakage current
Output is tri-stated
Output enable mode
Output is power down
spread
spread
A
B
C
D
E
F
± 0.125%
± 0.250%
± 0.375%
± 0.500%
± 0.625%
± 0.750%
± 0.875%
± 1.000%
I
± 1.125%
± 1.250%
± 1.375%
± 1.500%
± 1.625%
± 1.750%
± 1.875%
± 2.000%
K
M
O
P
R
S
T
G
H
Table 1
auris-GmbH office@auris-gmbh.de www.auris-gmbh.de
All specifications are subject to change without notice.
4.14
AURIS [ AURIS-GMBH ]
